Length: 3 Days (24 hours)
Digital Badges
Course Description
This comprehensive course emphasizes the essential stages of the Analog IC Design flow, focusing on enhancing designer productivity by effectively utilizing the latest features available in the Virtuoso® Studio platform. Starting from the initial referencing of the PDK, you will gain insights into creating the design schematic and symbol, followed by the creation and simulation of the testbench. Subsequently, you will delve into circuit layout design, physical verification, and parasitic extraction processes. The course will cover a comprehensive understanding of the Analog front-to-back flow, including the process of exporting the layout to GDSII format.
Learning Objectives
After completing this course, you will be able to:
- Set up the required PDK with the Virtuoso Studio Design Environment
- Design a schematic from the transistor level using the Virtuoso Schematic Editor
- Create testbench setup and simulation environments using the Virtuoso ADE Explorer and Assembler
- Perform pre-layout and post-layout simulations using the Spectre® circuit simulator and analyze them using the Virtuoso VA window
- Tune the design parameters using the Real-Time Tuning assistant to meet the specifications
- Generate a layout from the schematic using the Auto Place & Route (Auto P&R) assistant and perform routing
- Debug and clear the DRC and LVS errors using the Pegasus™ Verification System and iPegasus™ Verification System for Virtuoso Studio
- Perform Parasitic Extraction from the layout using the Quantus™ Extraction Solution
- Generate the GDSII file for tapeout
Software Used in This Course
- Virtuoso Studio IC23.1
- Spectre 23.1
- Pegasus 23.2
- Quantus23.1
Software Release(s)
IC23.1 ISR8, Spectre23.1 ISR8, PEGASUS23.2, QUANTUS23.1
Modules in this Course
- Schematic Design and Symbol Creation
- Schematic Testbench and Modifying DUT Parameters
- Pre-Layout Simulation
- Layout Design
- Physical Verification
- Parasitic Extraction, Post-Layout Simulation, and Generating GDSII
Audience
This course is intended for:- Designers who are new to Virtuoso or those who would like an overview of the complete analog IC design flow using the latest Cadence® tools.
- College/University graduates who want to learn the Cadence tools flow.
- Also, this course will be a revision for:
- Analog IC Design Engineers
- Mixed-Signal Design Engineers
- Analog Physical Designers
Prerequisites
Before taking this course, you must:
- Have knowledge of Linux commands
- Have a good understanding of analog circuit design concepts
- Hava a good understanding of device physics and the IC fabrication process
- Have good problem-solving skills
Related Courses
- Virtuoso Schematic Editor
- Virtuoso ADE Explorer and Assembler S1: ADE Explorer and Single Test Corner Analysis
- Virtuoso ADE Explorer and Assembler S2: ADE Assembler and Multi Test Corner Analysis
- Spectre Simulator Fundamentals S1: Spectre Basics
- Virtuoso Layout Design Basics
- Virtuoso Layout Pro: T3 Basic Commands
- Virtuoso Layout Pro: T4 Advanced Commands
- Virtuoso Layout Pro: T5 Interactive Routing
- Virtuoso Layout for Advanced Nodes
- Auto Place and Route (APR) for Virtuoso Studio – Device Level
- Pegasus Verification System
- Quantus Transistor-Level T2: Parasitic Extraction
