Auto Place and Route (APR) for Virtuoso Studio – Device Level Training
Date | Version | Country | Location | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
Version | Region | |
---|---|---|
IC23.1 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length: 2 Days (16 hours)
Digital Badges
Course Description
The placement and routing solution in the Virtuoso® Studio makes it easy to create accurate analog and custom digital Device-Level layouts on advanced-process nodes. It includes intelligent device grouping, precise controls for device array placement, row-based and non-uniform grid-based device snapping, and advanced cell fill to automatically create symmetrical analog device placement. It also features automated routing on width spacing-based track patterns with support for mesh routing structures, which simplifies complex wiring for a large number of series/parallel devices in FinFET process technology.
The Virtuoso Automated Device Placement and Routing flow automatically generates layouts that comply with constraints, are LVS correct, and adhere to DRCs. It is designed for analog and mixed signal device-level designs using advanced node PDKs. The flow uses the Auto P&R assistant for device placement and the Routing assistant for device routing.
This course is designed to equip designers with the necessary skills for Device-Level Placement, Initialize and Plan a Layout, Device Placement Using the Auto Place and Route Assistant, and Automated Device-Level Routing for the Virtuoso Studio.
Learning Objectives
After completing this course, you will be able to:
- Understand the APR Workspace and assistant in doing Placement and Routing.
- Identify important terms in the Virtuoso Placement and Routing flow
- Set up Auto Device Placement and Routing workspace
- Create a layout in the Automated Device Placement
- Use the APR workspace to do placement and routing
- Apply Device Placement using the Auto P&R assistant
- Analyze interactive placement commands
- Examine generating constraints and constraint groups
- Illustrate how to configure Device-Level Router settings
- Verify layout routability after generating grids and running the device placer
- Analyze generating Pin-to-Trunk Routing for selected nets
- View and analyze Device-Level Routing results
Software Used in This Course
Virtuoso Studio IC 23.1
Software Release(s)
IC 23.1
Modules in this Course
- Device-Level Placement
- Initialize and Plan a Layout
- Device Placement Using the Auto Place and Route Assistant
- Virtuoso Automated Device-Level Routing
Audience
- Physical Designers
- Layout Engineers
Prerequisites
You must have experience with or knowledge of the following:
- Virtuoso Layout Suites XL and EXL
Or you must have completed the following course:
Related Courses
- Virtuoso Layout Design Basics
- Virtuoso Layout for Advanced Nodes: T1 Place and Route
- Virtuoso Layout for Advanced Nodes: T2 Electromigration
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.