The formal fundamental course is intended for people with little or no experience in Formal Analysis (FA) and Jasper™. This course pragmatically illustrates how to code efficient SVA properties for formal analysis. Formal analysis is an entirely different paradigm from older and more widely adopted verification methods, such as simulation. As such, the fundamental objectives, capabilities, limitations, setup, initialization requirements, and analysis and interpretation of results must be well understood before we can effectively use Formal tools and specialized Jasper Apps. Formal is capable of much more than simulation alone and can deliver optimization techniques that often need to be applied to get conclusive results within realistic timescales. These techniques are complicated to discover or pick up "as one goes along" without training or expert assistance. Anyone can run a Formal tool, but experience is needed to get conclusive results in a realistic, wholly understood timeframe. This course is intended as a shortcut to gaining that experience. The course has 60% lectures and 40% hands-on labs.
The SystemVerilog Assertions or SVA course gives you an in-depth introduction to SystemVerilog Assertions (SVA), together with guidelines and methodologies to help you create, manage, and debug effective assertions for complex design properties. The course is packed with examples, case studies, and hands-on lab exercises to demonstrate real-life applications of SVA using both simulation and formal techniques. Different approaches to coding assertions and reuse issues are also examined.
