Length: 10 Days (80 hours)
Become Cadence Certified
Course Description
Become Cadence-Certified in the Signoff Timing and Power Analysis domain by taking a curated series of our online courses and passing the badge exams for each class.
- First, we learn how to run simulations and related tasks using Cadence® Xcelium™ Simulator.
- Then, we go through the entire RTL2GDSII flow using Cadence Tools in each of the phases.
- We then jump to the most crucial part of the verification flow, the coverage aspects and analysis using Cadence Integrated Metrics tool.
- Then, we learn the the concept and the task of debugging using Cadence Verisium™ Debug tool.
- Then, we learn the process of verification planning and management using the Cadence Verisium Manager tool.
Learning Objectives
After completing the certification program, you will learn about:
- Simulating a design using the Xcelium simulator and its related tasks
- Entire RTL2GDSII flow using Cadence Tools in each of the phases in the flow
- Performing Coverage Analysis
- Performing Debug for your designs
- Coverage gaps and Verification closure
After completing the certification program, you will be able to:
- Perform simulation using the Cadence Xcelium simulator tool for design verification and debugging
- Use the different commands of Xcelium simulator, starting with xrun with relevant options, to invoke the simulator, along with the SimVision™ tool GUI interface, for simulating and debugging any given design in both Single-Core and Multi-Core modes
- Code a design in Verilog to the design specification that is provided
- Compile, elaborate and simulate your design
- Synthesize your design
- Design for test
- Run equivalency checking at different stages of the flow
- Floorplan a design
- Run placement, optimization, clock tree synthesis, and routing on your design
- Run signoff checks to make sure that the design chip can be fabricated
- Write out a GDSII
- Effectively use the Xcelium integrated coverage with your VHDL, Verilog, and mixed-language designs
- Debug designs using Cadence Verisium Debug
- using Xcelium™ Simulator for simulation
- Debug any given design efficiently using advanced features of the Verisium Debug
- Use the commands of the Verisium Debug, starting with appropriate options, to invoke the Verisium Debug GUI interface
- Identify tricks and efficient ways to debug testbench and RTL designs faster
- Define and review the Cadence Metric Driven Verification (MDV) methodology
- Use the MDV in a verification project
- Recognize the importance of verification planning and develop a vPlan
- Explore the vManager tool and identify the various centers
- Set up the server profile for the vManager server
- Use vManager Planning to create a verification plan (vPlanx) format
- Apply a reusable vPlan
- Create a regression run with a Verification Session Input File (VSIF)
- Explore Metrics analysis using the Analysis Center
- Run regressions using vManager and map coverage
- Analyze metrics and perform coverage correlation and ranking
- Recognize the usefulness of the Web dashboard, vAPI, Sever Security Authentication and Authorization
- Generate project reporting and charting in tracking centers
Software Used in This Course
This certification program contains several courses, each with its own software requirements. Refer to each of the course links provided in the course description and course contents for the specifics.
Software Release(s)
Each course URL contains the software release information for that course
Modules in this Course
Audience
- Electronics or Computer Engineering students
- CAD Engineers
- Place and Route Engineers
- Design Engineers
- ASIC Designers
- Chip Designers
Prerequisites
You must have experience with or knowledge of the following:
- Programming
- Electronics or Computer Engineering
Related Courses
Course ID: 86357
