Length: 123 hours
Become Cadence Certified
Course Description
Become Cadence-certified in the Design and Verification Language and Methodology domain by taking a curated series of our online courses and passing the badge exams for each course.
- First, we provide a high-level overview of semiconductors and the EDA industry with the
Semiconductor 101 course
- Then, learn about the fundamentals of the digital design flow with the
- First, we provide detailed learning of Verilog as a design and verification language with labs.
- Then, we switch to the industry's latest SystemVerilog design and verification language constructs with labs.
- We then jump to the most adopted verification methodology in the industry, the universal verification methodology or the UVM course with excellent labs.
Learning Objectives
After completing the certification program, you will learn about:
- Moore's Law and its impact on the chip's performance, manufacturing process, and costs
- How chip design is different from other types of design
- Verilog language and its application in design and verification streams
- SystemVerilog language and its application in design and verification streams
- UVM as a verification methodology
After completing the certification program, you will be able to:
- Draw a flow diagram of the entire design flow and explore the entire ASIC design flow process
- Identify the distinction between Digital IC design, verification, and implementation
- Recognize the different stages of front-end design and verification
- Use fundamental Verilog constructs to create a simple design
- Ensure that Verilog designs meet the requirements for synthesis
- Develop Verilog test environments of significant capability and complexity
- Understand and use the SystemVerilog RTL design and synthesis features, including new data types, literals, procedural blocks, statements, and operators, relaxation of Verilog language rules, fixes for synthesis issues, enhancements to tasks and functions, new hierarchy and connectivity features, and interfaces
- Use the SystemVerilog RTL design and synthesis features, including new data types, literals, procedural blocks, statements, and operators, relaxation of Verilog language rules, fixes for synthesis issues, enhancements to tasks and functions, new hierarchy and connectivity features, and interfaces
- Understand the features and capabilities of the UVM class library for SystemVerilog
- Create, configure and customize reusable, scalable, and robust UVM Verification Components (UVCs)
- Combine multiple UVCs into a complete verification environment
- Integrate scoreboards, multichannel sequencers, and register models
Software Used in This Course
This certification program contains several courses, each with its own software requirements. Refer to each of the course links provided in the course description and course contents for the specifics.
Software Release(s)
Each course URL contains the software release information for that course.
Modules in this Course
Audience
- Electronics or Computer Engineering students
- CAD Engineers
- Place and Route Engineers
- Design Engineers
- ASIC Designers
- Chip Designers
Prerequisites
You must have experience with or knowledge of the following:
- Programming
- Electronics or Computer Engineering
Related Courses
Course ID: 86356
