Length: 9.5 Days (76 hours)
Become Cadence Certified
Course Description
Become Cadence-Certified in the digital physical design domain by taking a curated series of our online courses and passing the badge exams for each class.
- First, we provide a high-level overview of semiconductors and the EDA industry with the Semiconductor 101 course.
- Then, learn about the fundamentals of the digital design flow with the Digital IC Design Fundamentals course.
- Next, you will learn the complete RTL2GDS flow using Cadence tools with the Cadence RTL-to-GDSII Flow.
- In the Basic Static Timing Analysis course, you learn the concepts of static timing analysis and apply them to constrain a design and analyze timing reports.
- In the Innovus Block Implementation with Stylus Common UI course, you learn how to run floorplanning, placement optimization, clock-tree synthesis, and routing optimization to achieve the best power, performance, and area (PPA) for your design
- Finally, in the Innovus Hierarchical Implementation with Stylus Common UI course, you create partitions (hierarchical blocks), run place-and-route, and optimize the design (at the block level and top level) to close timing.
Learning Objectives
After completing the courses, you will learn about:
- Moore's law and its impact on the chip's performance, manufacturing process, and costs
- How chip design is different from other types of design
- Systems, stacked dies, and how emulation and prototyping are used before fabrication
- Semiconductor markets
- Cadence Intelligent Design Strategy
- The design flow with Cadence EDA tools
- How the industry transitioned from fabs to fabless companies
After completing the courses, you will be able to:
- Draw a flow diagram of the entire design flow and explore the entire ASIC design flow process
- Identify the distinction between Digital IC design, verification, and implementation
- Recognize the different stages of front-end design and verification
- Demonstrate the SystemVerilog HDL for design and verification
- Recognize the different stages of design implementation
- Create, verify, and implement a system-level design with a simple architecture
- Identify the challenges of scaling, costs, and physical attributes, as well as low power and area constraints before tapeout
- Identify the different processes in the semiconductor industry used to handle the above realistic challenges
- Code a design in Verilog to the design specification that is provided
- Compile, elaborate and simulate your design
- Synthesize your design
- Design for test
- Run equivalency checking at different stages of the flow
- Floorplan a small design
- Run placement, optimization, clock tree synthesis, and routing on your design
- Run signoff checks to make sure that the design chip can be fabricated
- Write out a GDSII
- Identify and apply timing arc information from a library, including unateness, delays, and slew
- Identify cell delays from a library and calculate output slew degradation
- Use wire-load information to calculate net delays
- Identify the properties of a clock, including period, edges, slew, and duty cycle
- Apply setup and hold checks to diagnose design violations
- Identify timing path types and calculate slack values
- Set design-level and environmental constraints
- Set timing constraints, including clocks and external delays
- Set path exceptions
- Analyze reports to identify timing problems
- Import and explore interactive floorplanning options
- Place the standard cells and blocks in the design
- Run power planning, power routing, and power analysis
- Reorder scan chains
- Analyze routing congestion
- Extract parasitics and generate timing reports
- Create clock trees
- Optimize and close timing
- Analyze how to optimize routing with technology (LEF) and design files
- Route critical nets with shielding and spacing
- Edit wires using the interactive wire editor
- Analyze and fix routing violations
- Report and fix timing and signal integrity violations
- Implement an Engineering Change Order (ECO)
- Explore the Stylus flow to implement your design
- Floorplan and create partitions for your hierarchical design
- Run pin placement and route busses
- Create and use ILMs
- Prototype a design using blackboxes, FlexModels and SoC Architecture Information technology
- Run the Integrated Hierarchical Database (iHDB) flow for implementation
Software Used in This Course
This certification program contains several courses, each with its own software requirements. Refer to each of the course links provided in the course description and course contents for the specifics.
Software Release(s)
Each course URL contains the software release information for that course.
Modules in this Course
Audience
- Electronics or Computer Engineering students
- CAD Engineers
- Place and Route Engineers
- Design Engineers
- ASIC Designers
- Chip Designers
Prerequisites
You must have experience with or knowledge of the following:
- Programming
- Electronics or Computer Engineering
Related Courses
Course ID: 86354
