Length: 9.5 Days (76 hours)
Become Cadence Certified
Course Description
Become Cadence-certified in the synthesis and static timing analysis domain by taking a curated series of our online courses and passing the badge exams for each course.
- First, we provide a high-level overview of semiconductors and the EDA industry with the Semiconductor 101 course.
- Then, learn about the fundamentals of the digital design flow with the Digital IC Design Fundamentals course.
- Next, you will learn the complete RTL2GDS flow using Cadence tools with the Cadence RTL-to-GDSII Flow.
- In the Basic Static Timing Analysis course, you learn the concepts of static timing analysis and apply them to constrain a design and analyze timing reports.
- In the Genus Synthesis Solution with Stylus Common UI training course, you learn several techniques to constrain a design, run static timing analysis, evaluate datapath logic, and run physical synthesis.
- Finally, in the Advanced Synthesis with Stylus Common UI course, you debug problems in the synthesis of complex designs when optimizing for timing, area, and power.
Learning Objectives
After completing the certification program, you will learn about:
- Moore's Law and its impact on the chip's performance, manufacturing process, and costs
- How chip design is different from other types of design
- Systems, stacked dies, and how emulation and prototyping are used before fabrication
- Semiconductor markets
- Cadence Intelligent Design Strategy
- The design flow with Cadence EDA tools
- How the industry transitioned from fabs to fabless companies
After completing the certification program, you will be able to:
- Draw a flow diagram of the entire design flow and explore the entire ASIC design flow process
- Identify the distinction between Digital IC design, verification, and implementation
- Recognize the different stages of front-end design and verification
- Demonstrate the SystemVerilog HDL for design and verification
- Recognize the different stages of design implementation
- Create, verify, and implement a system-level design with a simple architecture
- Identify the challenges of scaling, costs, and physical attributes, as well as low power and area constraints before tapeout
- Identify the different processes in the semiconductor industry used to handle the above realistic challenges
- Code a design in Verilog to the design specification that is provided
- Compile, elaborate, and simulate your design
- Synthesize your design
- Design for test
- Run equivalency checking at different stages of the flow
- Floorplan a design
- Run placement, optimization, clock tree synthesis, and routing on your design
- Run signoff checks to make sure that the design chip can be fabricated
- Write out a GDSII
- Identify and apply timing arc information from a library, including unateness, delays, and slew
- Identify cell delays from a library and calculate output slew degradation
- Use wire-load information to calculate net delays
- Identify the properties of a clock, including period, edges, slew, and duty cycle
- Apply setup and hold checks to diagnose design violations
- Identify timing path types and calculate slack values
- Set design-level and environmental constraints
- Set timing constraints, including clocks and external delays
- Set path exceptions
- Analyze reports to identify timing problems
- Explore the features of the Genus™ Stylus Common User Interface
- Apply the recommended synthesis flow using the Cadence® Genus Synthesis Solution
- Explore MMMC and how to set up and update the MMMC configuration of a design
- Debug design scenarios
- Use the extended datapath features
- Optimize designs using the physical synthesis flow
- Analyze and synthesize the design for low-power structures
- Constrain the design for testability (DFT)
- Identify the interface to Conformal® Equivalence Checker and other tools
- Identify Flowkit and Unified Metrics
- Identify Unified Safety Format
- Identify Genus Synthesis Solution flow
- Set up and update MMMC configuration of a design
- Analyze the log file to debug and fix the timing of a design
- Apply retiming to fix the timing of a complex block
- Identify best practices for synthesizing complex designs
- Identify the setup for Genus Physical with low-power and DFT Flow
- Apply multi-bit cell inferencing
- Identify the Interface Logic Model
- Analyze physical synthesis results
- Verify designs using Conformal Equivalence Checker
Software Used in This Course
This certification program contains several courses, each with its own software requirements. Refer to each of the course links provided in the course description and course contents for the specifics.
Software Release(s)
Each course URL contains the software release information for that course.
Modules in this Course
Audience
- Electronics or Computer Engineering students
- CAD Engineers
- Place and Route Engineers
- Design Engineers
- ASIC Designers
- Chip Designers
Prerequisites
You must have experience with or knowledge of the following:
- Programming
- Electronics or Computer Engineering
Related Courses
None
Course ID: 86353
