Length: 9.5 Days (76 hours)
Become Cadence Certified
Course Description
Become Cadence-Certified in the Signoff Timing and Power Analysis domain by taking a curated series of our online courses and passing the badge exams for each class.
- First, we provide a high-level overview of semiconductors and the EDA industry with the Semiconductor 101 course.
- Then, learn about the fundamentals of the digital design flow with the Digital IC Design Fundamentals course.
- Next, you will learn the complete RTL2GDS flow using Cadence tools with the Cadence RTL-to-GDSII Flow.
- In the Basic Static Timing Analysis course, you learn the concepts of static timing analysis and apply them to constrain a design and analyze timing reports.
- In the Tempus Signoff Analysis with Stylus Common UI course, you will analyze a design for static timing and signal integrity issues inherent in advanced process nodes. You also run signoff timing analysis to analyze timing issues on large designs and fix timing issues.
- In the Voltus Power Grid Analysis and Signoff with Stylus Common UI course, you will learn static and dynamic power and rail analysis and early rail analysis. You identify different IR-aware ECO optimization techniques and develop a chip package co-design model.
Learning Objectives
After completing the courses, you will learn about:
- Moore's law and its impact on the chip's performance, manufacturing process, and costs
- How chip design is different from other types of design
- Systems, stacked dies, and how emulation and prototyping are used before fabrication
- Semiconductor markets
- Cadence Intelligent Design Strategy
- The design flow with Cadence EDA tools
- How the industry transitioned from fabs to fabless companies
After completing the courses, you will be able to:
- Draw a flow diagram of the design flow and explore the entire ASIC design flow process
- Identify the distinction between Digital IC design, verification, and implementation
- Recognize the different stages of front-end design and verification
- Demonstrate the SystemVerilog HDL for design and verification
- Recognize the different stages of design implementation
- Create, verify, and implement a system-level design with a simple architecture
- Identify the challenges of scaling, costs, and physical attributes, as well as low power and area constraints before tapeout
- Identify the different processes in the semiconductor industry used to handle the above realistic challenges
- Code a design in Verilog to the design specification that is provided
- Compile, elaborate and simulate your design
- Synthesize your design
- Design for test
- Run equivalency checking at different stages of the flow
- Floorplan a design
- Run placement, optimization, clock tree synthesis, and routing on your design
- Run signoff checks to make sure that the design chip can be fabricated
- Write out a GDSII
- Identify and apply timing arc information from a library, including unateness, delays, and slew
- Identify cell delays from a library and calculate output slew degradation
- Use wire-load information to calculate net delays
- Identify the properties of a clock, including period, edges, slew, and duty cycle
- Apply setup and hold checks to diagnose design violations
- Identify timing path types and calculate slack values
- Set design-level and environmental constraints
- Set timing constraints, including clocks and external delays
- Set path exceptions
- Analyze reports to identify timing problems
- Explore the features of the Tempus™ Stylus Common User Interface
- Identify timing analysis data requirements and import Single Corner designs and Multi-Mode Multi-Corner (MMMC) designs
- Identify and apply timing debug techniques using the Global Timing Debug interface
- Analyze a design for timing combined with signal integrity (SI)
- Compare parallel processing techniques such as Concurrent MMMC, Distributed MMMC and Distributed STA
- Run ECO analysis and timing closure flow between the Stylus Innovus™ Implementation and the Stylus Tempus Signoff tools
- Identify the features and capabilities of the Voltus IC Power Integrity Solution
- List the data import methods and run design data “sanity” checks
- Execute Early Rail Analysis to detect problems in the power grid in the early stages of the design
- Generate power-grid libraries for power-grid analysis
- Set up and run Static and Dynamic Power and Rail Analysis
- Analyze and plot power and rail results
- Identify IR Aware ECO techniques to mitigate IR drop issues
- Develop a chip package co-design model
Software Used in This Course
This certification program contains several courses, each with its own software requirements. Refer to each of the course links provided in the course description and course contents for the specifics.
Software Release(s)
Each course URL contains the software release information for that course.
Modules in this Course
Audience
- Electronics or Computer Engineering students
- CAD Engineers
- Place and Route Engineers
- Design Engineers
- ASIC Designers
- Chip Designers
Prerequisites
You must have experience with or knowledge of the following:
- Programming
- Electronics or Computer Engineering
Related Courses
Course ID: 86352
