Designing with Integrity 3D-IC Training

Length: 2 Days (16 hours)

Become Cadence Certified

Course Description

This course introduces Integrity^™ 3D-IC, the industry's first comprehensive, high-capacity 3D-IC platform that integrates 3D design planning, implementation, and system analysis in a single, unified environment. You will be guided through the following activities involved in designing a silicon interposer with a digital ASIC and HBM2 interface in a 2.5D configuration.

• You will design the interposer from scratch in the new Integrity System Planner and the Integrity 3D-IC implementation environment.
• You will examine the ASIC and interposer designs using some of the new 3D-IC multi-die design features.
• You will route the interposer using some of the new advanced routing capabilities with NanoRoute^™

Learning Objectives

After completing this course, you will be able to:

• Create the Interposer device and import the ASIC and HBM devices in Integrity 3D-IC System Planner.
• Perform top-level integration and placement of the HBMs, ASIC, and Interposer in Integrity 3D-IC System Planner.
• Perform netlist creation, signal assignment, and bump and TSV creation for the Interposer in Integrity 3D-IC System Planner.
• Push both the ASIC and Interposer designs to Integrity 3D-IC Layout for implementation.
• Route the Interposer design in Integrity 3D-IC Layout.

Software Used in This Course

• Integrity 3D IC (INTG100)
• Innovus 3D IC Option (INVS60)

Software Release(s)

INNOVUS221

Modules in this Course

• Creating the Interposer
• Importing the ASIC and HBM Die
• Floorplanning the Die on the Interposer
• Importing or Creating the Interposer Netlist
• Creating the Interposer Contact Pads and Die Connectivity
• Defining Power and Ground Net Classes
• Creating the Interposer to Package Substrate C4 Bumps
• Adding Through Silicon Vias for the C4 Bumps
• Routing the Interposer Design with Integrity 3D-IC Layout

Audience

• This course is intended for IC designers focused on Interposer and 3D-IC designs from a Cadence cross-platform solution point of view.
• It is also intended for users who would like to understand the 3D/2.5D IC design process.

Prerequisites

You must have experience with or knowledge of the following:

• Routing principles
• Signal integrity
• Power integrity
• IC principles

Related Courses

• OrbitIO System Planner
• Allegro Package Designer Plus

Free Online Training Bytes (Videos)