Digital IC Design Fundamentals Training

Length: 2 1/4 Day (18 hours)

Course Description

Note: This course is highly recommended for onboarding new employees (including recent college graduates) to ramp up on the complete Tool-Agnostic Digital IC Design flow.

DICDF is a basic yet complete overview of IC design flow, a tool-agnostic course. It starts by explaining the entire IC design flow as a flow diagram, touching on each phase in the flow and explaining the practical challenges in the IC industry. It then goes on to the concepts of Digital IC functional design, including hardware concepts, low-power concepts, and SystemVerilog coding, followed by functional verification on the front end. Lastly, it covers the back end and sign-off sections with synthesis, place and route, implementation, and Digital sign-off, followed by IC packaging concepts.

Learning Objectives

After completing this course, you will be able to:

• Draw a flow diagram of the entire design flow and explore the entire ASIC design flow process
• Identify the distinction between Digital IC design, verification, and implementation
• Recognize the different stages of front-end design and verification
• Demonstrate the SystemVerilog HDL for design and verification
• Recognize the different stages of design implementation
• Create, verify, and implement a system-level design with a simple architecture
• Identify the challenges of scaling, costs, and physical attributes, as well as low power and area constraints before tapeout
• Identify the different processes in the semiconductor industry used to handle the above realistic challenges

Software Used in This Course

• XCELIUM2403

Software Release(s)

X300

Modules in this Course

Module1

• About This Course

Module2

• Digital IC Design Flow – Overview and Challenges
  • The Scale of the Challenge

Module3

• Digital IC Functional Design
  • Digital IC Functional Design: Hardware Implementation
  • Data Representation
  • Combinatorial Building Blocks
  • Clocked Building Blocks and Synchronous Design
  • Arithmetic Building Blocks
  • Finite State Machines
  • Memory Structures
• Functional Design Challenges
  • X-Propagation
  • Clock Domain Crossing (CDC)
  • Reset Domain Crossing (RDC)
  • Clock Gating
• Low-Power Concepts
  • Introduction to Low-Power Simulation

Module 4

• SystemVerilog Fundamentals for Design
  • Design Modules
  • Standard SystemVerilog Types
  • Making Procedural Statements
  • Using Operators
  • Using Blocking and Nonblocking Assignments
  • User-Defined Data Types and Structures
  • Packages
  • Coding RTL for Synthesis
  • Designing Finite State Machines

Module 5

• Functional Verification
  • Debug Techniques
  • Debugging Using Interactive Debug with Xcelium: GUI and Textual/Batch Commands
  • Introduction to a Modern Verification Flow
  • Introduction to MDV and Planning
  • Overview of Formal Analysis Use Models
  • The Verification Completeness Problem

Module 6

• Digital IC Design Methodology
  • Logic Synthesis
  • Design for Test (DFT)
  • Joint Test Action Group (JTAG)
  • Floorplanning
  • Placement
  • Physical Synthesis
  • Static Timing Analysis
  • Clock Tree Synthesis
  • Pre-and Post-CTS Optimization
  • Routing
  • Extraction
  • Delay Calculation
  • Timing Analysis
  • IRdrop Analysis
  • Design Verification
  • Mask Prep

Module 7

• IC Packaging
  • IC Packaging Styles
  • IC Package Implementation Process
  • PDN for DC Voltage Drop
  • PDN for AC Impedance Across a Frequency Spectrum
  • 3D-EM Analysis to Generate an S-Parameter Model
  • Thermal Performance of the IC Package

Audience

• Electrical / Computer Science Engineering students working towards a bachelor's or master's degree
• Entry-level engineers or recent college graduates in the EDA industry in design, verification, or implementation domain roles

Prerequisites

You must have experience and knowledge of the following:

• Basic programming

You must have completed the following:

• Semiconductor 101

Related Courses

• SystemVerilog for Design and Verification

• Cadence RTL-to-GDSII Flow Training

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.