Conformal Low Power Verification Using IEEE 1801 Training

Length: 1 Day (8 hours)

Become Cadence Certified

Course Description

In this course, you learn to verify low-power designs using Conformal^® Low-Power Verification. In the labs, you debug practical examples of IEEE 1801 violations, functional and structural violations, and nonequivalences.

Learning Objectives

After completing this course, you will be able to:

• Identify features of the Conformal Low-Power software
• Identify the flows for low-power verification
• Identify power intent support in the Conformal Low-Power software
• Apply low-power checks on gate netlists with corresponding power intent
• Apply low-power checks on physical netlists with corresponding power intent
• Run low-power equivalency checks in different stages along with the supplied power intent

Software Used in This Course

• Conformal Low Power XL

Software Release(s)

CONFRML241

Modules in this Course

• Overview
• Preparation and Setup
• Power Intent Support (IEEE 1801)
• Synthesis Verification
• Physical Verification
• Using Conformal Low-Power Effectively

Audience

• ASIC Designers
• Logic Designers
• Hardware Engineers
• FPGA Designers
• Digital IC Designers
• Design Engineers

Prerequisites

 You must have experience with or knowledge of the following:

• Have a basic understanding of Verilog language and constructs
• Have a basic understanding of either UPF or IEEE 1801 power intent formats
• Completed Logic Equivalence Checking with Conformal course or
• Have equivalent experience with the Conformal Equivalence Checker tool

Or you must have completed the following course:

• Conformal Equivalence Checking

Related Courses

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