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Sigrity Aurora
Date | Version | Country | Location | |
---|---|---|---|---|
27 - 29 Jun 2022 | 17.4QIR4 | France | EMEA-Blended-France France |
ENROLL |
27 - 29 Jun 2022 | 17.4QIR4 | Germany | EMEA-Blended-Germany Germany |
ENROLL |
27 - 29 Jun 2022 | 17.4QIR4 | Israel | EMEA-Blended-Israel Israel |
ENROLL |
27 - 29 Jun 2022 | 17.4QIR4 | United Kingdom Of Great Britain And Northern Ireland | EMEA-Blended-UK United Kingdom Of Great Britain And Northern Ireland |
ENROLL |
18 - 20 Oct 2022 | 17.4QIR4 | Germany | Feldkirchen-Munich Germany |
ENROLL |
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
Version | Region | |
---|---|---|
17.4QIR4 | Online | ENROLL |
17.4QIR2 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length: 3 Days (24 hours)
Digital Badge Available
Course Description
In this course, you use the Sigrity™ Aurora software to develop design rules for high-speed designs. You add the resulting physical and electrical constraints to the design through topology templates. These constraints drive the routing of nets on the printed circuit board. You run preroute and postroute signal simulations to analyze the PCB for reflection, crosstalk, IR Drop, and other high-speed design factors. You also use the Power Feasibility Editor to derive a decoupling capacitor scheme and create Power Integrity Constraint Sets to drive the placement of the decoupling capacitors.
Learning Objectives
After completing this course, you will be able to:
- Create, extract and explore topologies
- Run solution space analysis
- Create an electrical constraint set
- Apply constraints to drive placement and routing
- Analyze nets on the routed board design for signal integrity
- Use the Workflow Manager to analyze impedance, crosstalk and IR Drop on a PCB
- Use the Power Feasibility Editor to create Power Integrity Constraint Sets
Software Used in This Course
Sigrity AuroraSoftware Release(s)
SPB17.4QIR4
Modules in this Course
- Introduction to Sigrity Aurora
- Topology Extraction
- Topology Explorer Basics
- SPICE and Trace Models in TopXplorer
- Source Synchronous Sweep Simulations with TopXplorer
- Constraint Floorplanning
- In Design Analysis Workflows
- Using the IR Drop Workflow
- Power Feasibility Editor
- Power Integrity Constraint Sets
Audience
- Electrical Engineers
- PCB Designers
Prerequisites
You must have:
- A familiarity with digital and analog circuit design methodology
- A working knowledge of PCB signal analysis and transmission line theory
Related Courses
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
Free Online Training Bytes (Videos)