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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • Allegro X Design Platform
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  • Tensilica FloatingPoint DSP Family



Tensilica FloatingPoint DSP Family

Online Courses
Version Region
9.6 Online ENROLL
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Length: 2 days (16 Hours)

Course Description

The focus of this training class is the Tensilica® FloatingPoint DSP Family.

This class provides an overview of the Tensilica FloatingPoint DSP architecture, instruction set, and programming model. It includes information on common Tensilica FloatingPoint DSP operations, how to write and optimize code, and how to use the advanced capabilities of the XT-CLANG C/C++ compiler. It provides essential skills necessary to develop and optimize baseband, radar/lidar, image processing, and neural network algorithms and kernels on the Tensilica FloatingPoint DSPs.

This class includes labs to give practical and hands-on experience with the DSP core, libraries, and software tools.

Learning Objectives

After completing this course, you will be able to:

  • Understand the Tensilica FloatingPoint DSP architecture, instruction set, and programming model
  • Write and optimize C/C++ programs for VLIW/SIMD machines like the Tensilica FloatingPoint DSPs
  • Use the advanced capabilities of the XT-CLANG C/C++ compiler to generate efficient compiled code
  • Use the library routines provided with the Tensilica FloatingPoint DSPs to accelerate your software development cycle

Software Used in This Course

  • Tensilica Xtensa® Xplorer RI-2021.6
  • Tensilica Xtensa Software Tools RI-2021.6

Software Release(s)

RI-2021.6

Modules in this Course

About This Course

  • Tensilica FloatingPoint DSP Family Overview
    • Application Performance
    • Architecture Overview
    • Instruction Set Highlights
    • Data Handling
  • Programming Styles
    • The N-Programming Model
    • Auto-Vectorization of Scalar C Code
    • C Operators with Vector Types
    • Intrinsics Use
    • DSP Libraries
    • Lab 3-1 – Vector Programming
  • Programming Guidelines
    • Lab 4-1 – Auto-Vectorization
  • FloatingPoint DSP Family Instruction Overview  
    • Vector Element Operations
    • Load and Store Operations
    • Multiply Operations
    • Lab 5-1 – Intrinsic Optimization
  • Advanced Topics
    • Vector Floating-Point
    • Matrix Multiply
    • Divide, Reciprocal, SQRT, RSQRT
    • FIR Support
    • FFT Support
    • Gather/Scatter Support
    • Lab 6-1 – Packed Matrix Multiplication
  • Next Steps
    • Q/A

Audience

  • Software developers and firmware engineers writing and optimizing code for the FloatingPoint DSP Family

Prerequisites

You must have experience with or knowledge of the following:

  • Programming in C for embedded processors or DSPs

Or, you must have completed the following courses:

  • Tensilica Xtensa LX Processor Fundamentals
  • Tensilica Xtensa NX Processor Fundamentals

Related Courses

  • Tensilica ConnX BBE32EP Baseband Engine
  • Tensilica ConnX B10 DSP
  • Tensilica Fusion G3 DSP
  • Tensilica Vision Q7 DSP

Click here to view course learning maps, and here for complete course catalogs.

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Course ID: 86280

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