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        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
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          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
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        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
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          • Layout Verification
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          • Spectre X Simulator
          • Virtuoso RF Solution
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          • Virtuoso ADE Product Suite
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          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation and Prototyping
          • Formal and Static Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
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          • System / Peripherals IP
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          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Omnis
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          • AWR Free Trial
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  • Tensilica Xtensa Neural Network Compiler v2



Tensilica Xtensa Neural Network Compiler v2

Online Courses
Version Region
9.4 Online ENROLL
Other Verions Online EXPRESS INTERESTINQUIRE

Length : 1/2 day

Course Description

This course introduces the Xtensa Neural Network Compiler (XNNC) v2.

The purpose of the Xtensa® Neural Network Compiler (XNNC) is to convert a floating-point Convolutional Neural Network (CNN) into an optimized, fixed-point solution for Cadence Tensilica® processors. The course aims to guide the user to the effective use of configuring and running supported neural network models through the different stages and modes of the XNNC workflow. This includes how to configure inputs and outputs for a network and the usage of the Custom Operator Application Interface (API).  

The course describes the added support for Graph Lowering (Glow) Compiler techniques, Tensorflow convertors, Open Neural Network eXchange (ONNX), and Caffe2. The course also explains the use of new Quantization schemes and Xtensa Exchange Formats for generated DSP codes.

Learning Objectives

After completing this course, you will be able to:

  • Configure and run the supported neural network models through different stages and modes of the XNNC workflow.
  • Understand the use of new Quantization schemes and Xtensa Exchange Formats for generated DSP codes.

Software Used in This Course

  • Xtensa Neural Network Compiler (XNNC) v2.0 forWindows or Linux

Software Release(s)

Xtensa Software Tools release RI-2020.4, Xtensa Xplorer 8.0.13

Modules in this Course

  • About This Course
  • XNNC Inputs
  • XNNC Outputs
  • Customer Operations

Audience

  • Software Engineers and Architects 
  • Neural Network Architects
  • Machine Learning Researchers

Prerequisites

You must have experience with or knowledge of the following:

  • Machine Learning, Computer Vision and Imaging Concepts
  • Neural Network Frameworks (specifically Caffe2, OnnX and Tensorflow)
  • Some familiarity with DSP Processors and Embedded Programming
You must have completed one of the following courses:
  • Tensilica Xtensa LX Processor Fundamentals
OR
  • Tensilica Xtensa NX Processor Fundamentals

Related Courses

  • Tensilica Xtensa LX Processor Fundamentals
  • Tensilica Xtensa NX Processor Fundamentals
Course ID: 86277

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