Length :Estimated 5 days (27 modules + lab exercises)
Semiconductor ICs and SoCs increasingly include both digital and analog IP. As such, mixed-signal verification is a sign-off requirement and accurate, high-speed models are needed to achieve that. IEEE 1800 SystemVerilog includes constructs to support these models known collectively as Real Number Modeling (SV-RNM).
This advanced course consists of 27 video modules and associated code examples for the lab exercises that will provide you with comprehensive SV-RNM modeling knowledge. The videos explain the key concepts and demonstrate tool and model operation. Associated lab exercises challenge you to apply your new knowledge in real design situations. In total, the course covers fundamental techniques of modeling analog and RF behaviors, modeling applications in a variety of common circuit types, top-down design and verification methodologies, and the proper use of advanced SystemVerilog language capabilities in mixed signal system verification.
After completing this course, you will be able to
Understand the features and capabilities of SV-RNM for the creation of accurate, high-speed Digital Mixed-Signal (DMS) models. You will be able to code models for several circuit types and have the foundational knowledge for more sophisticated modeling.
Software Used in This Course
XCELIUM 19.09 (19.09-s002), IC 6.1.8 -64b.83
Modules in this Course
- Modules 1-3 introduce why modeling is needed, the syntax of SV-RNM, and modeling best practices.
- Modules 4-6 introduce modeling for specific circuit types including filters, gain circuits, signals, ADCs, DACs, and signal sources.
- Modules 7-10 introduce EEnet UDNs and provide detailed information for their application to circuit modeling.
- Modules 11-18 provide guidance for modeling a variety of circuit types including PLLs, RF nets, linear regulators, and RF mixers.
- Modules 19-20 add modeling support concepts including sampling methods and instrumenting analog measurements.
- Modules 21-24 focus on verification including the use of SV assertions, real randomization, real coverage, and managing model abstractions.
- Modules 25-27 describe advanced concepts including a comparison of Verilog-AMS and SV-RNM, simulation performance optimization, and modeling for designs with power intent defined by IEEE-1801 (UPF).
- Analog, mixed-signal, Digital Designers and Verification Engineers, System Verification Engineers.
You must have:
- Experience with SystemVerilog
It is recommended that you have completed the following course: