Length : 2 days
Course Description
This is an Engineer Explorer series course. The Engineer Explorer courses explore advanced topics.
This course is intended for users of JasperGold® wishing to improve Formal Verification Performance by using advanced techniques. There is a 50/50 split between lectures and hands-on labs which allows the user to gain experience of the advanced techniques discussed in the course. Advanced property development techniques are shown with numerous real-life code examples utilizing techniques such as non-determinism, relaxing checks, reducing formal complexity in general and for liveness properties and fairness constraints,data tagging and more. In addition, how to detect, debug and fix over-constraining arising from conflicts and deadends are discussed. The course also covers how to make abstractions and reductions of the DUT to improve formal performance and how to use tool features to understand where design complexity is coming from and hence address how to reduce it. Finally, the course teaches methods of how to couple a design abstraction with a specialized checker to achieve better performance. Implementation of different kinds of formal scoreboards are discussed: for example, CAM tables and Fuzzy Scoreboards.
Learning Objectives
After attending the course, you will be able to:
- Write simple and efficient assertions with a small complexity footprint
- Write effective deadlock assertions with both safety and liveness semantics
- Recognize and deal with deadends and conflicts in a formal environment
- Identify the different complexities in a formal testbench
- Apply abstraction and reduction techniques to deal with the complexities of a formal testbench
- Create formal friendly checkers using checker abstraction techniques
- Apply checker abstraction techniques to deliver an efficient Formal Scoreboard
Software Used in This Course
- JasperGold
- VIP Catalog (VIPCAT113)
Software Release(s)
JASPER2003 VIPCAT11.3-069
Modules in this Course
- Advanced Property Development
- Non-determinism
- Data tagging
- Relaxed checks
- Forward progress
- Liveness
- Conflict & Dead-End Detection and Debug
- Design Abstraction and Reduction
- Abstraction vs. Reduction
- Identify complexity hot spots
- Case split
- Design reductions
- Cutpoints and abstract models
- Hot-starting: Initial-value Abstractions (IVAs)
- Coupling Design & Checker Abstraction
- Checker Abstraction
- Coupling abstractions with checkers
- Location-based Abstractions
- Signature-based Abstractions
- Combining Location and Signature methods
- Formal Scoreboards
Audience
Verification Engineers and Designers who wish to use advanced techniques in order to improve Formal Verification Performance
Prerequisites
Before starting the course, there is a requirement for 2-3 hours self-study to become familiar with the Packet Processor Design used in the course lab exercises. Time is not available during the course for this familiarization. Cadence will provide those materials 7 days prior to your course starting.In addition, you must have 3 months of experience with SVA and JasperGold
OR
You must have completed one of the following courses:
Related Courses
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
Course ID: 86268
