Pegasus Verification System

Length : 2 days

Digital Badge Available

Course Description

With the exponential increase in design rule check (DRC) complexity at advanced nodes, existing DRC solutions have not been able to support the turnaround requirements to ensure design schedules are met. The Cadence^® Pegasus^™ Verification System is a cloud-ready physical verification signoff solution with an innovative architecture that delivers up to 10X improved performance on DRC runs, which enables engineers to deliver advanced-node integrated circuits (ICs) to market faster. Customers can now achieve complete full-chip signoff DRC on advanced-node designs in a matter of hours, helping designers deliver products to market faster, or easily run multiple DRC signoff iterations, if needed, at the time of tapeout.

This course has been designed for user-level physical design verification, where you run DRC, LVS, ERC, PERC, FastXOR and Pegasus Interactive checks to find and debug layout errors that are located in your design. You set up options, run Pegasus checks, and use Pegasus Results Viewer or other appropriate error browsers to locate and fix design rule violations. You set up, run and debug LVS and ERC violations including shorts and stamping conflicts. Interactive Shorts Locator (ISL), Probing form or Graphical LVS Debugger are used to spot shorting locations. You then set up and run Pegasus Interactive in Verify-Design mode for in-design instant DRC checking, and use FastXOR to compare a stream file with an existing OpenAccess cellview.

In this course, the Virtuoso^® Layout Suite is used where the Pegasus Verification System is integrated to the Virtuoso menus for easy access.

Learning Objectives

After completing this course, you will be able to:

• Identify the features and Advance Debug solutions in Pegasus
• Set up and run Pegasus DRC, ERC, LVS, PERC and FastXOR in GUI and batch modes
• Debug DRC in Pegasus Results Viewer and LVS in the Pegasus LVS debug environment
• Explore the Pegasus Configurator feature
• Check the Pegasus QuickView platform
• Define and debug stamping conflicts
• Debug Pegasus LVS with Interactive Short Locator and GLD
• Set up and run Pegasus Interactive in Verify Design mode
• Create and manage snapshots for Pegasus Interactive
• Review Pegasus tips and reference info on Cadence Online Support

Software Used in This Course

• Virtuoso Layout Suite
• Pegasus Verification System

Software Release(s)

PEGASUS194, ICADV123

Modules in this Course

• Pegasus Introduction
• Design Rule Checking
• Electrical Rules Checking
• Programmable ERC
• Layout Versus Schematic
• Pegasus Interactive
• Running FastXOR
• Extended Practice for DRC and LVS

Audience

• Physical layout designers who need to verify layout designs

Prerequisites

You must have:

• Knowledge and experience with physical design and verification

• Familiarity with the Virtuoso Layout Suite

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