Length : 2 days
Course Description
With the exponential increase in design rule check (DRC) complexity at advanced nodes, existing DRC solutions have not been able to support the turnaround requirements to ensure design schedules are met. The Cadence® Pegasus™ Verification System is a cloud-ready physical verification signoff solution with an innovative architecture that delivers up to 10X improved performance on DRC runs, which enables engineers to deliver advanced-node integrated circuits (ICs) to market faster. Customers can now achieve complete full-chip signoff DRC on advanced-node designs in a matter of hours, helping designers deliver products to market faster, or easily run multiple DRC signoff iterations, if needed, at the time of tapeout.
This course has been designed for user-level physical design verification, where you run DRC, LVS, ERC, PERC, FastXOR and Pegasus Interactive checks to find and debug layout errors that are located in your design. You set up options, run Pegasus checks, and use Pegasus Results Viewer or other appropriate error browsers to locate and fix design rule violations. You set up, run and debug LVS and ERC violations including shorts and stamping conflicts. Interactive Shorts Locator (ISL), Probing form or Graphical LVS Debugger are used to spot shorting locations. You then set up and run Pegasus Interactive in Verify-Design mode for in-design instant DRC checking, and use FastXOR to compare a stream file with an existing OpenAccess cellview.
In this course, the Virtuoso® Layout Suite is used where the Pegasus Verification System is integrated to the Virtuoso menus for easy access.
