Length: 2 days (16 Hours)
Digital Badge Available
Course Description
With the exponential increase in design rule check (DRC) complexity at advanced nodes, existing DRC solutions have not supported the turnaround requirements to ensure design schedules are met. The Cadence® Pegasus™ Verification System is a cloud-ready physical verification signoff solution with an innovative architecture that delivers up to 10X improved performance on DRC runs, enabling engineers to deliver advanced-node integrated circuits (ICs) to market faster. Customers can now achieve complete full-chip signoff DRC on advanced-node designs in a matter of hours, helping designers deliver products to market more quickly, or efficiently run multiple DRC signoff iterations, if needed, at the time of tapeout.
This course has been designed for user-level physical design verification. You run DRC, LVS, ERC, PERC, FastXOR, and Pegasus Interactive checks to find and debug layout errors in your design. You set up options, run Pegasus checks, and use Pegasus Results Viewer to locate and fix design rule violations. You set up, run and debug LVS and ERC violations, including shorts and stamping conflicts. Interactive Shorts Locator (ISL), Probing form, and Pegasus Layout/Schematic Netlist Viewer are used to spot shorting locations. You then set up and run Pegasus Interactive in Verify-Design mode for in-design instant DRC checking, and use FastXOR to compare a stream file with an existing OpenAccess cell view.
In this course, the Virtuoso® Layout Suite is used where the Pegasus Verification System is integrated into the Virtuoso menus for easy access.
Pegasus Cadence and Learning Support Landing Page: Pegasus™ Verification System
NOTE: This course is compatible with IC 6.1.8 and ICADVM 20.1
Learning Objectives
After completing this course, you will be able to:
- Identify the features and Advance Debug solutions in Pegasus
- Set up and run Pegasus DRC, ERC, LVS, PERC and FastXOR in GUI and batch modes
- Debug DRC, ERC, LVS, PERC and FastXOR violations in Pegasus Results Viewer
- Explore the Pegasus Configurator feature
- Check the Pegasus Design Review (PDR) platform
- Define and debug stamping conflicts
- Debug LVS shorts with Pegasus Interactive Short Locator (ISL)
- Set up and run Pegasus Interactive in Verify Design mode
- Create and manage snapshots for Pegasus Interactive
- Review Pegasus tips and reference info on Cadence Learning and Support
Software Used in This Course
- Virtuoso Layout Suite
- Pegasus Verification System
Software Release(s)
PEGASUS 21.2, IC 6.1.8, ICADVM 20.1
Modules in this Course
- Pegasus Introduction
- Design Rule Checking
- Electrical Rules Checking
- Programmable ERC (Optional)
- Layout Versus Schematic
- Pegasus Interactive
- Running FastXOR (Optional)
- Extended Practice for DRC and LVS (Optional)
Audience
- Physical layout designers who need to verify layout designs
Prerequisites
You must have:
- Knowledge and experience with physical design and verification
- Familiarity with the Virtuoso Layout Suite
Related Courses
- SystemVerilog for Design and Verification
- Virtuoso Schematic Editor
- Virtuoso Layout Design Basics
- Virtuoso Connectivity-Driven Layout Transition
- Physical Verification System
- Physical Verification Language Rules Writer
- Assura Verification
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
