Length: 2 Days (16 hours)
Digital Badge Available
Course Description
The Cadence® Pegasus™ Verification System is a cloud-ready physical verification signoff solution, which enables engineers to deliver advanced-node integrated circuits (ICs) to market faster. The groundbreaking technology delivers up to 10X improved performance on DRC runs and reduces turnaround time from days to hours. The Pegasus system's innovative architecture and True Cloud processing provide an elastic and flexible computing environment. The Pegasus system provides a massively parallel architecture. It is the first solution to combine a pipelined infrastructure with stream processing delivering near-linear scalability across 100s of CPUs. The Pegasus system's Giga scale technology enables full-chip signoff DRC in just a few hours versus days.
The Pegasus system seamlessly integrates with the industry-standard Cadence Virtuoso® custom/analog platform, the market-leading Cadence Innovus™ Implementation System, Allegro®, and mixed-signal flows.
This course has been designed for user-level physical design verification. You run DRC, LVS, ERC, PERC, FastXOR, and Pegasus Interactive checks to find and debug layout errors in your design. You set up options, run verification, and use Pegasus Results Viewer to locate, analyze, and fix the violations. Under LVS checks, you debug shorts and stamping conflicts, using features like Interactive Shorts Locator (ISL), Probing form, and Stamping Conflict Debugger. You then set up and run Pegasus Interactive in Verify Design mode for in-design instant DRC checking, and use FastXOR to compare a stream file with an existing OpenAccess cell view.
In this course, the Virtuoso Layout Suite is used for layout design access, where the Pegasus Verification System comes integrated. This course is compatible with Virtuoso versions, IC 6.1.8 and ICADVM 20.1
You can visit Cadence and Learning Support Landing Page: Pegasus™ Verification System to know more about Pegasus.
Learning Objectives
After completing this course, you will be able to:
- Identify the features and Advance Debug solutions in Pegasus
- Set up and run Pegasus DRC, ERC, LVS, PERC, and FastXOR in GUI and batch modes
- Debug DRC, ERC, LVS, PERC, and FastXOR violations in Pegasus Results Viewer
- Explore the Pegasus Configurator feature
- Check the Pegasus Design Review (PDR) platform
- Define and debug stamping conflicts
- Debug LVS shorts with Pegasus Interactive Short Locator (ISL)
- Set up and run Pegasus Interactive in Verify Design mode
- Create and manage snapshots for Pegasus Interactive
- Review Pegasus tips and reference info on the Cadence Learning and Support
Software Used in This Course
- Virtuoso Layout Suite
- Pegasus Verification System
Software Release(s)
PEGASUS 22.1, IC 6.1.8, ICADVM 20.1
Modules in this Course
- Pegasus Introduction
- Design Rule Checking
- Electrical Rules Checking
- Programmable ERC (Optional)
- Layout Versus Schematic
- Pegasus Interactive
- Running FastXOR (Optional)
- Extended Practice for DRC and LVS (Optional)
Audience
- Physical layout designers who need to verify layout designs
Prerequisites
You must have:
- Knowledge and experience with physical design and verification
- Familiarity with the Virtuoso Layout Suite
Related Courses
- SystemVerilog for Design and Verification
- Virtuoso Schematic Editor
- Virtuoso Layout Design Basics
- Virtuoso Connectivity-Driven Layout Transition
- Physical Verification System
- Physical Verification Language Rules Writer
- Assura Verification
- Quantus Transistor-Level T1: Overview and Technology Setup
- Quantus Transistor-Level T2: Parasitic Extraction
- Quantus Transistor-Level T3: Extracted View Flows and Advanced Features
