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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • Allegro X Design Platform
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
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        • Hyperscale Computing
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        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
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        • Automotive
        • Hyperscale Computing
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  • Pegasus Verification System



Pegasus Verification System

Online Courses
Instructor-Led Schedule
Date Version Country Location
07 - 08 Nov 2022 21.2 France Vélizy-Paris
France
ENROLL
Scheduled upon demandOn demand EXPRESS INTERESTINQUIRE
Version Region
21.2 Online ENROLL
20.3 Online ENROLL
Other Versions Online EXPRESS INTERESTINQUIRE

Length: 2 days (16 Hours)

Digital Badge Available

Course Description

With the exponential increase in design rule check (DRC) complexity at advanced nodes, existing DRC solutions have not supported the turnaround requirements to ensure design schedules are met. The Cadence® Pegasus™ Verification System is a cloud-ready physical verification signoff solution with an innovative architecture that delivers up to 10X improved performance on DRC runs, enabling engineers to deliver advanced-node integrated circuits (ICs) to market faster. Customers can now achieve complete full-chip signoff DRC on advanced-node designs in a matter of hours, helping designers deliver products to market more quickly, or efficiently run multiple DRC signoff iterations, if needed, at the time of tapeout.

This course has been designed for user-level physical design verification. You run DRC, LVS, ERC, PERC, FastXOR, and Pegasus Interactive checks to find and debug layout errors in your design. You set up options, run Pegasus checks, and use Pegasus Results Viewer to locate and fix design rule violations. You set up, run and debug LVS and ERC violations, including shorts and stamping conflicts. Interactive Shorts Locator (ISL), Probing form, and Pegasus Layout/Schematic Netlist Viewer are used to spot shorting locations. You then set up and run Pegasus Interactive in Verify-Design mode for in-design instant DRC checking, and use FastXOR to compare a stream file with an existing OpenAccess cell view.

In this course, the Virtuoso® Layout Suite is used where the Pegasus Verification System is integrated into the Virtuoso menus for easy access.

Pegasus Cadence and Learning Support Landing Page: Pegasus™ Verification System 

NOTE: This course is compatible with IC 6.1.8 and ICADVM 20.1

Learning Objectives

After completing this course, you will be able to:

  • Identify the features and Advance Debug solutions in Pegasus
  • Set up and run Pegasus DRC, ERC, LVS, PERC and FastXOR in GUI and batch modes
  • Debug DRC, ERC, LVS, PERC and FastXOR violations in Pegasus Results Viewer
  • Explore the Pegasus Configurator feature
  • Check the Pegasus Design Review (PDR) platform
  • Define and debug stamping conflicts 
  • Debug LVS shorts with Pegasus Interactive Short Locator (ISL)
  • Set up and run Pegasus Interactive in Verify Design mode
  • Create and manage snapshots for Pegasus Interactive
  • Review Pegasus tips and reference info on Cadence Learning and Support

Software Used in This Course

  • Virtuoso Layout Suite
  • Pegasus Verification System

Software Release(s)

PEGASUS 21.2, IC 6.1.8, ICADVM 20.1

Modules in this Course

  • Pegasus Introduction
  • Design Rule Checking
  • Electrical Rules Checking
  • Programmable ERC (Optional)
  • Layout Versus Schematic
  • Pegasus Interactive
  • Running FastXOR (Optional)
  • Extended Practice for DRC and LVS (Optional)

Audience

  • Physical layout designers who need to verify layout designs

Prerequisites

You must have:

  • Knowledge and experience with physical design and verification
  • Familiarity with the Virtuoso Layout Suite

Related Courses

  • SystemVerilog for Design and Verification
  • Virtuoso Schematic Editor
  • Virtuoso Layout Design Basics
  • Virtuoso Connectivity-Driven Layout Transition
  • Physical Verification System
  • Physical Verification Language Rules Writer
  • Assura Verification
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Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.

Course ID: 86267

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