Innovus Low-Power Flow with Stylus Common UI

Length: 1 day (8 Hours)

Digital Badge Available

Course Description

Note: This course is based on the Stylus Common UI. Please consult with your Cadence AE before deciding to take this course instead of the course called Low-Power Flow with Innovus Implementation System, which is based on the default UI and not on the Stylus UI.

In this course, you explore and implement several low-power techniques to reduce both dynamic and leakage power during synthesis and design implementation. You run formal verification to ensure the functionality of a low-power design.

Learning Objectives

After completing this course, you will be able to:

• Implement Multi-Supply Multi-Voltage (MSMV) regions to reduce power consumption
• Implement a low-power clock tree
• Run concurrent timing, MSV optimization, and multi-VT (leakage) optimization
• Implement MSMV-aware detail routing
• Analyze data and debug power problems at different stages of the flow

Software Used in This Course

• Innovus Implementation System

Software Release(s)

INNOVUS211

Modules in this Course

• Introduction
• Power Reduction
• Implementing Low-Power Using Innovus Technology
• Floorplanning and Placement of Low-Power Cells
• Power Planning and Power Routing
• Leakage and Dynamic Power Optimization
• Power-Domain-Aware Routing
• Verifying a Low-Power Design
• Power Shutoff Domain Implementation
• Signoff Considerations for Low-Power Design

Audience

• ASIC Designers
• Chip Designers
• Digital IC Designers

Prerequisites

You must have experience with or knowledge of the following:

• Design methodology
• Innovus Implementation System software
• Fundamentals of IEEE 1801 Low-Power Specification Format

Related Courses

You must have experience with or knowledge of the following:

• Innovus Block Implementation with Stylus Common UI
• Fundamentals of IEEE 1801 Low-Power Specification Format

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