Length: 1 day
Course Description
Note: This course is based on the Stylus Common UI. Please consult with your Cadence AE before deciding to take this course instead of the course called Low-Power Flow with Innovus Implementation System, which is based on the default UI and not on the Stylus UI.
In this course, you explore and implement several low-power techniques to reduce both dynamic and leakage power during synthesis and design implementation. You run formal verification to ensure the functionality of a low-power design.
Learning Objectives
After completing this course, you will be able to:
- Implement Multi-Supply Multi-Voltage (MSMV) regions to reduce power consumption
- Implement a low-power clock tree
- Run concurrent timing, MSV optimization, and multi-VT (leakage) optimization
- Implement MSMV-aware detail routing
- Analyze data and debug power problems at different stages of the flow
Software Used in This Course
Software Release(s)
INNOVUS201
Modules in this Course
- Introduction
- Power Reduction
- Implementing Low-Power Using Innovus Technology
- Multi-Mode Multi-Corner View Definitions
- Introduction to IEEE 1801 Low-Power Specification Format
- Creating Physical Power Domain
- Level-Shifter and Isolation Cells
- Power Planning and Power Routing
- Leakage and Dynamic Power Optimization
- Power-Domain-Aware Routing
- Verifying a Low-Power Design
- Power Shutoff Domain Implementation
- Signoff Considerations for Low-Power Design
Audience
- ASIC Designers
- Chip Designers
- Digital IC Designers
Prerequisites
You must have experience with or knowledge of the following:
- Design methodology
- Place and route
Related Courses
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
