Length: 1 day (8 Hours)
Course Description
This one day training session teaches the basics of creating, configuring, and debugging a system simulation using Xtensa® SystemC (XTSC) and its associated component library models. We cover how to build a single Xtensa system in XTSC and run an application program. We show how to connect Xtensa with transaction level, pin level as well as TLM2 interfaces. In addition, we demonstrate how to cosimulate between Xtensa core in SystemC and other system componets in RTL. The four labs cover the different topics of system modeling using XTSC. This is an essential class for an engineer building system simulation models using Tensilica® processor cores.
Learning Objectives
After completing this course, you will be able to:
- Build a system model using XTSC
- Debug target running on the system using Xplorer
- Connect Xtensa core using pin level or TLM2 interfaces
- Cosimulation Xtensa core in SystemC and other IPs in RT
Software Used in This Course
- Xtensa Software Tools Release RI-2019.0
Software Release(s)
Modules in this Course
- Introduction to XTSC
- Course Objectives and Agenda
- What is XTSC
- XTSC differentiation
- Basic XTSC
- XTSC environment setup
- XTSC useful commands
- Run the first program using xtsc-run
- Simulation result in XTSC.log
- XTSC documents
- XTSC and Xtensa Tools
- Connect debugger to system simuluation
- Profiling software running on system simulation
- Integrating xtsc_core into SystemC Simulation
- Instantiate Xtensa core in sc_main
- Run the first program in SystemC simulation
- Pin level connection
- TLM2 connection
- How XTSC component is implemented
- XTSC and RTL Cosimulation
- Setup for RTL cosimulation
- Cosim Examples
- How to load a program for RTL cosimulation
- How to get help
Audience
- Engineers building or working with SystemC based simulation models of Tensilica processor cores
Prerequisites
You must have completed the following course:
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