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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation and Prototyping
          • Formal and Static Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
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          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Omnis
          • Sigrity Advanced SI
          • Sigrity Advanced PI
          • RESOURCES
          • System Analysis Resources Hub
          • AWR Free Trial
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          • Augmented Reality Lab Tools
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  • Command-Line Based Mixed-Signal Simulations with the Xcelium Use Model



Command-Line Based Mixed-Signal Simulations with the Xcelium Use Model

Instructor-Led Schedule
Date Version Country Location
09 Jun 2021 18.09 Germany Feldkirchen-Munich
Germany
ENROLL
Scheduled upon demandOn demand EXPRESS INTERESTINQUIRE

Length : 1 day

Course Description

In this course, you use the mixed-signal, mixed-language Spectre® AMS Designer Simulator and Xcelium™ mixed signal capabilities. You use the command-line based Xcelium use model that uses the xrun executable.
You are introduced to the mixed-signal simulation and debugging capabilities of the SimVision™ tool that allows you to view interactive waveforms.
In the text-based command-line flow, you use different control files and control cards in sync with a single-step xrun command.
You also discuss SystemVerilog and other HDL testbench reuse and bus mapping.
For verifying designs, you learn the interoperability across SystemVerilog, SystemC and the AMS Designer.
Finally, the AMS Designer support for the Common Power Format (CPF) and IEEE 1801 Unified Power Format (UPF) are discussed.

Learning Objectives

After completing this course, you will be able to:

  • Learn discipline resolution and connect rules/connect modules usage that is required for mixed-signal interface translations
  • Simulate mixed-signal designs with the Spectre AMS Designer/Xcelium mixed-signal simulators using command-line control
  • Learn to run simulations and debug them using the SimVision Interactive debugger
  • Simulate with a single-step xrun command, learn to use its associated control files
  • Use the Unified Power Format (UPF) and the Common Power Format (CPF) to insert power smart connect modules
  • Apply verification flows using SystemVerilog and SystemC

Software Used in This Course

  • 70060 Spectre AMS Connector
  • 70070 Spectre AMS Designer
  • X300 Xcelium Single Core
  • X310 Xcelium DMSO
  • 90005 Spectre Multi Mode Simulation with AMS

Software Release(s)

Xcelium 18.09, Spectre 18.1

Modules in this Course

  • Mixed Signal Discipline Resolution and Connect Module Concepts (Optional)
  • SimVision for Interactive Debugging of Simulations
  • Using Spectre AMS Designer in a Text-Based Command-Line Flow
  • Design Verification and Managing Multiple Power Domains During AMS Simulations

Audience

  • Analog/Mixed-Signal IC Designers
  • Analog/Mixed-Signal Verification Engineers

Prerequisites

 

You must have experience with or knowledge of the following:

  • Using Spectre AMS Designer with the Xcelium DMS Option

Or you must have completed the following course:

  • Mixed-Signal Simulations Using Spectre AMS Designer

 

Related Courses

Replace this paragraph with a bulleted list of any related courses linked to their datasheets.
Following is an example course and link.

  • Mixed-Signal Simulations Using Spectre AMS Designer
  • Mixed-Signal IP and Testbench Reuse Model

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.

Course ID: 86244

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