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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • Allegro X Design Platform
          • RESOURCES
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        • Hyperscale Computing
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        • Mixed Signal
        • Photonics
        • RF / Microwave
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        • Hyperscale Computing
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  • Allegro EDM Design Entry HDL Front-to-Back Flow



Allegro EDM Design Entry HDL Front-to-Back Flow

Online Courses
Instructor-Led Schedule
Date Version Country Location
11 - 13 Jul 2022 17.4-2019QIR2 Sweden Kista-Stockholm
Sweden
ENROLL
11 - 13 Jul 2022 17.4-2019QIR2 United Kingdom Of Great Britain And Northern Ireland Bracknell-London
United Kingdom Of Great Britain And Northern Ireland
ENROLL
Scheduled upon demandOn demand EXPRESS INTERESTINQUIRE
Version Region
17.4-2019QIR2 Online ENROLL
17.2-2016QIR6 Online ENROLL
Other Versions Online EXPRESS INTERESTINQUIRE

Length: 3 days (24 Hours)

Course Description

In this course, you create board-level schematic designs with Design Entry HDL from within the Allegro® EDM environment. You explore the integration between Design Entry HDL and other tools in the design flow, including the Allegro PCB Editor. You follow the design flow by creating a schematic and taking it all the way through board layout.

Although board layout is introduced as part of the front-to-back flow, this is not a board layout course. Also, schematic or footprint library development is not included in this course. See the Related Courses below.

Learning Objectives

After completing this course, you will be able to:

  • Set up new projects
  • Create a flat, multisheet design
  • Check the design
  • Package a design
  • Create and customize a Bill of Materials
  • Build a hierarchical design
  • Use schematic properties to control part placement
  • Use the Constraint Manager to define high-speed routing requirements in Design Entry HDL
  • Transfer the design to the PCB Editor
  • Place parts manually
  • Auto-route with the PCB Router
  • Compare the schematic and layout
  • Incorporate engineering changes

All from within the Allegro EDM Environment

Software Used in This Course

  • Allegro Design Authoring (PS2000)
  • Allegro Design Authoring with High Speed Option (PA1410)
  • Allegro PCB Designer (PA3100)
  • Allegro Library Server (PDW703)
  • Allegro Data Manager (PDW504)
  • Allegro Library Manager (PDW624)

Software Release(s)

SPB17.2-2016QIR6 or later

Modules in this Course

  • Getting Started
  • Project Setup
  • Design Entry and Packaging
  • Hierarchical Design
  • Design Rules
  • Rules-Driven Layout
  • Engineering Changes
  • Debugging Problems

Audience

  • Design Engineers
  • PCB Layout Designers

Prerequisites

This course has no prerequisites.

Related Courses

  • Allegro High-Speed Constraint Management
  • Allegro PCB Editor Basic Techniques
  • Allegro PCB Librarian

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.

Course ID: 86240

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