Length: 2 days (16 Hours)
This is an Engineer Explorer series course. The Engineer Explorer courses explore advanced topics.
This is a lecture-only class.
In this course, you will integrate and use Cadence® VIP in the Verification environment. You also understand how to use various VIP features to enable efficient debugging and reduce the time required to verify the design. VIP contains features such as callbacks, functional coverage, error injection capability and various other debugging capabilities along with the a basic test suite for each protocol.
After completing this course, you will be able to:
- Understand Cadence VIP architecture
- Integrate VIP to the custom verification environment
- Use the various features of VIP for effective debug
Software Used in This Course
Modules in this Course
- VIP Architecture Overview
- VIP Topologies Overview
- VIP Integration: UVM Config Flow
- Writing VIP Tests
- VIP Callbacks
- VIP Messaging and Debugging
- VIP Coverage
- VIP Error Injection
- Verification Engineers
You must have experience with or knowledge of the following
- SystemVerilog language usage
- UVM or any other verfication methodology