Voltus Power Grid Analysis and Signoff with Stylus Common UI

Length: 2 Days (16 hours)

Digital Badge Available

Course Description

Note: This course is based on the Stylus Common UI. Please consult with your design team or Cadence AE before selecting this course instead of the Voltus™ Power-Grid Analysis and Signoff course, which is based on the default UI. If there is not a clear preference, please select this course.

This is an Engineer Explorer course for designers who need a comprehensive and detailed understanding of power-rail analysis for advanced processes.

In this two-day course, you explore the need for power-rail analysis and use the Cadence^® Voltus^™ IC Power Integrity Solution with Stylus CUI software to run static and dynamic power and rail analysis. On the first day, you import design data and run some design sanity checks. You also run early rail analysis using the Innovus^™ Stylus Implementation System. You then create the technology library and power-grid view libraries. On the second day, you run static power and rail analysis. You also run dynamic power and rail analysis and analyze the results. You identify different IR-aware ECO optimization techniques and develop chip package co-design model. 

Learning Objectives

After completing this course, you will be able to:

• Identify the features and capabilities of the Voltus™ IC Power Integrity Solution
• List the data import methods and run design data “sanity” checks
• Execute Early Rail Analysis to detect problems in the power grid in the early stages of the design
• Generate power-grid libraries for power-grid analysis
• Set up and run Static and Dynamic Power and Rail Analysis
• Analyze and plot power and rail results
• Identify IR Aware ECO techniques to mitigate IR drop issues
• Develop a chip package co-design model 

Software Used in This Course

• Voltus IC Power Integrity Solution with Stylus CUI
• Innovus Implementation System with Stylus CUI

Software Release(s)

SSV211, INNOVUS211

Modules in this Course

• Introduction to Voltus IC Power Integrity Solution in Stylus CUI Mode
• Design Data Importing and Sanity Checks
• Early Rail Analysis
• Power-Grid View Library Generation
• Static Power and Rail Analysis
• Dynamic Power and Rail Analysis

Audience

• Analog/Mixed-Signal IC Designers
• Custom Circuit Designers
• Design Engineers
• Digital IC Designers
• IC Designers
• Place and Route Designers
• Verification Engineers

Prerequisites

You must have experience with:

• Digital place-and-route tools
• UNIX or Linux OS

Related Courses

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