Innovus Hierarchical Implementation with Stylus Common UI Training
Date | Version | Country | Location | |
---|---|---|---|---|
20 May 2025 | 23.1 | France | Vélizy-Paris France |
ENROLL |
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
Version | Region | |
---|---|---|
23.1 | Online | ENROLL |
22.1 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length: 1 Day (8 hours)
Become Cadence Certified
Course Description
Note: This course is based on the Stylus Common UI. Please consult your design team or Cadence AE before selecting this course instead of the Innovus™ Implementation System (Hierarchical) course, which is based on the default UI. If there is not a clear preference, please select this course.
In this course, you explore the features of the Innovus Implementation System software using the Stylus Common User Interface (UI) for creating and implementing a hierarchical design. You learn several techniques to floorplan your design, create partitions (hierarchical blocks), run place-and-route, and optimize the design (at the block level and top level) to close timing. You learn techniques to reduce memory size and run time using interface logic models (ILMs). You will also learn how to use blackboxes, FlexModels, and SoC Architecture Information technology to prototype a design when a complete netlist is not available and explore the benefits of using the Integrated Hierarchical Database (iHDB) flow to reduce memory, runtime, and TAT.
Learning Objectives
After completing this course, you will be able to:
- Floorplan and create partitions for your design
- Run pin placement and route busses
- Create and use ILMs
- Prototype a design using blackboxes, FlexModels and SoC Architecture Information technology
- Run the Integrated Hierarchical Database (iHDB) flow for implementation
Software Used in This Course
Digital Design and Implementation
The software includes Genus™ Synthesis Solution, Joules™, and the Innovus Implementation System.
Software Release(s)
DDI231
Modules in this Course
- Innovus Implementation System Overview
- Partitioning the Design
- Placing Pins
- Bus Planning
- Interface Logic Models (ILMs)
- Using Blackboxes, FlexModels and SoC Architecture Information (SAI) Prototyping Flows
- Integrated Hierarchical Database (iHDB) Flow
Audience
- ASIC Designers
- CAD Engineers
- Chip Designers
- Layout Designers
Prerequisites
You must have experience with or knowledge of:
- Design methodology
- Place-and-route
Related Courses
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.