Length : 1 day
Course Description
Note: This course is based on the Stylus Common UI. Please consult with your Cadence AE before deciding to take this course instead of the course called Innovus™ Implementation System (Hierarchical), which is based on the default UI and not on the Stylus UI.
In this course, you explore the features of the Innovus Implementation System software using the Stylus Common User Interface (UI) for creating and implementing a hierarchical design. You learn several techniques to floorplan your design, create partitions (hierarchical blocks), run place and route, and optimize the design (at the block level and top level) to close timing. You learn techniques to reduce the memory size and run time by using interface logic models (ILMs). You will also learn how to use blackboxes, FlexModels, and SoC Architecture Information technology to protoype a design when a complete netlist is not available.
Learning Objectives
After completing this course, you will be able to:
- Floorplan and create partitions for your design
- Run pin placement and route busses
- Create and use ILMs
- Prototype a design using blackboxes, FlexModels and SoC Architecture Information technology
Software Used in This Course
- Innovus Implementation System
Software Release(s)
INNOVUS191
Modules in this Course
- Innovus Implementation System Overview
- Partitioning the Design
- Placing Pins
- Bus Planning
- Interface Logic Models (ILMs)
- Using Blackboxes, FlexModels and SoC Architecture Information Prototyping Flows
Audience
- ASIC Designers
- CAD Engineers
- Chip Designers
- Layout Designers
Prerequisites
You must have experience with or knowledge of:
- Design methodology
- Place and route
Related Courses
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
