Length: 2 Days (16 hours)
Digital Badges
Course Description
Note: This course is based on the Stylus Common UI. Please consult with your design team or Cadence AE before selecting this course instead of the Tempus™ Signoff Timing Analysis and Closure course, which is based on the default UI. If there is not a clear preference, please select this course.
This course is a detailed exploration of the timing and signal integrity analysis capabilities of the Tempus Timing Signoff Solution with Stylus Common UI. In this course, you analyze a design for static timing and signal integrity issues that are inherent in advanced process nodes with feature sizes 90nm and below. You also run signoff timing analysis to analyze timing issues on large designs using Tempus™ ECO and fix timing issues using the Innovus™ Implementation System with Stylus CUI.
Learning Objectives
After completing this course, you will be able to:
- Explore the features of the Tempus Stylus Common User Interface
- Identify timing analysis data requirements and import Single Corner designs and Multi-Mode Multi-Corner (MMMC) designs
- Identify and apply timing debug techniques using the Global Timing Debug interface
- Analyze a design for timing combined with signal integrity (SI)
- Compare parallel processing techniques such as Concurrent MMMC, Distributed MMMC and Distributed STA
- Run ECO analysis and timing closure flow between the Stylus Innovus Implementation and the Stylus Tempus Signoff tools
Software Used in This Course
- Tempus Timing Signoff Solution with Stylus Common UI
- Innovus Implementation System with Stylus Common UI
Software Release(s)
SSV251, DDI251
Modules in this Course
- Introduction to the Tempus Timing Signoff Solution in Stylus Common UI Mode
- Design Import
- Timing Analysis and Reporting
- Timing Debug
- Crosstalk Analysis
- Parallel Processing
- Tempus ECO Flow
Audience
- Digital IC Designers
- IC Designers
- Place-and-Route Designers
Prerequisites
You must have an experience with or the knowledge of the following:
- Cadence physical design tools
- Static Timing Analysis
Related Courses
You must have completed the following courses:
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
“Very good, relevant and enjoyable as first time on blended learning. Nice mix of slides, videos and labs.” -Blended Training-
Andrew Muir, STMicroelectronics
"With this training we are able to improve our already existing tempus script a lot. Very good explanations and examples. I could follow and learn even if it's not an everyday topic for me. Perfect organization of the training."
Thomas Fina, NXP Semiconductors
"Good course showing Tempus improvements."
Kevin Doherty, INSIDE Secure
“Good course at the correct level for my experience (...) I feel I would now be able to run and debug basic timing issues in Tempus. I liked the level of information that was given in the slides and the labs were at a good standard for beginning to use Tempus.” -Blended Training-
Russell Forsyth, STMicroelectronics
“Good experience, have learnt many things. Good course, quite intensive; professional trainer with good knowledge of background and adjacent topics”
Leonid Yanovich, X-FAB Semiconductor Foundries
“The course fitted well to the expectation. The instructor added some company dedicated sections to fit our expectation. The labs are fast and well documented.” - Blended Training-
Michael Laine, STMicroelectronics
"I have got a very positive impression of the training. Very positive atmosphere with enough time for questions. The training came right on time as we are starting to work with Tempus ECO in the project."
Christian Joseph, NXP Semiconductors