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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • Allegro X Design Platform
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
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      • AI IP Portfolio
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        • Arm-Based Solutions
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        • RF / Microwave
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        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
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        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
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        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
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  • Tempus Signoff Timing Analysis and Closure with Stylus Common UI



Tempus Signoff Timing Analysis and Closure with Stylus Common UI

Online Courses
Instructor-Led Schedule
Date Version Country Location
27 Jun - 15 Nov 2022 21.1 United Kingdom Of Great Britain And Northern Ireland EMEA-Blended-UK
United Kingdom Of Great Britain And Northern Ireland
ENROLL
14 - 15 Nov 2022 21.1 France Vélizy-Paris
France
ENROLL
Scheduled upon demandOn demand EXPRESS INTERESTINQUIRE
Version Region
21.1 Online ENROLL
20.1 Online ENROLL
Other Versions Online EXPRESS INTERESTINQUIRE

Length: 2 days (16 Hours)

Digital Badge Available

Course Description

This course is a detailed exploration of the timing and signal integrity analysis capabilities of the Tempus™ Timing Signoff Solution with Stylus Common UI. In this course, you analyze a design for static timing and signal integrity issues that are inherent in advanced process nodes with feature sizes 90nm and below. You also run signoff timing analysis to analyze timing issues on large designs and fix timing issues using the Innovus™ Implementation System with Stylus CUI.

Learning Objectives

After completing this course, you will be able to:

  • Explore the features of the Tempus Stylus Common User Interface
  • Identify timing analysis data requirements and import Single Corner designs and Multi-Mode Multi-Corner (MMMC) designs
  • Identify and apply timing debug techniques using the Global Timing Debug interface
  • Analyze a design for timing combined with signal integrity (SI)
  • Compare parallel processing techniques such as Concurrent MMMC, Distributed MMMC and Distributed STA
  • Run ECO analysis and timing closure flow between the Stylus Innovus Implementation and the Stylus Tempus Signoff tools

Software Used in This Course

  • Tempus Timing Signoff Solution with Stylus Common UI
  • Innovus Implementation System with Stylus Common UI

Software Release(s)

SSV211, INNOVUS211

Modules in this Course

  • Introduction to the Tempus Timing Signoff Solution in Stylus Common UI Mode
  • Design Import
  • Timing Analysis
  • Timing Debug
  • Crosstalk Analysis
  • Parallel Processing
  • Tempus ECO Flow

Audience

  • Digital IC Designers
  • IC Designers
  • Place-and-Route Designers

Prerequisites

You must have an experience with or the knowledge of the following:

  • Cadence physical design tools
  • Static Timing Analysis

Related Courses

  • Tempus Signoff Timing Analysis and Closure
  • Innovus Digital Implementation (Block)

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.

Free Online Training Bytes (Videos)
Course ID: 86226

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“Very good, relevant and enjoyable as first time on blended learning. Nice mix of slides, videos and labs.” -Blended Training-

Andrew Muir, STMicroelectronics

"With this training we are able to improve our already existing tempus script a lot. Very good explanations and examples. I could follow and learn even if it's not an everyday topic for me. Perfect organization of the training."

Thomas Fina, NXP Semiconductors

"Good course showing Tempus improvements."

Kevin Doherty, INSIDE Secure

“Good course at the correct level for my experience (...) I feel I would now be able to run and debug basic timing issues in Tempus. I liked the level of information that was given in the slides and the labs were at a good standard for beginning to use Tempus.” -Blended Training-

Russell Forsyth, STMicroelectronics

“Good experience, have learnt many things. Good course, quite intensive; professional trainer with good knowledge of background and adjacent topics”

Leonid Yanovich, X-FAB Semiconductor Foundries

“The course fitted well to the expectation. The instructor added some company dedicated sections to fit our expectation. The labs are fast and well documented.” - Blended Training-

Michael Laine, STMicroelectronics

"I have got a very positive impression of the training. Very positive atmosphere with enough time for questions. The training came right on time as we are starting to work with Tempus ECO in the project."

Christian Joseph, NXP Semiconductors

 
 

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