Tempus Signoff Timing Analysis and Closure with Stylus Common UI

After completing this course, you will be able to:

• Explore the features of the Tempus Stylus Common User Interface
• Identify timing analysis data requirements and import Single Corner designs and Multi-mode Multi-corner (MMMC) designs
• Identify and apply timing debug techniques using the Global Timing Debug interface
• Analyze a design for timing combined with signal integrity (SI)
• Compare parallel processing techniques such as Concurrent and Distributed MMMC
• Run ECO analysis and timing closure flow between the Stylus Innovus Implementation and the Stylus Tempus Signoff tools

• Tempus Timing Signoff Solution with Stylus Common UI
• Innovus Implementation System with Stylus Common UI

• Introduction to the Tempus Timing Signoff Solution with Stylus Common UI
• Design Import and Tool Flow
• Preparing for Timing Analysis
• Timing Debug
• Crosstalk Analysis
• Parallel Processing
• Tempus ECO Flow

• Digital IC Designers
• IC Designers
• Place-and-Route Designers

You must have an experience with or the knowledge of the following:

• Cadence physical design tools
• Static Timing Analysis

• Tempus Signoff Timing Analysis and Closure
• Innovus Digital Implementation (Block)

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.