Length : 2 days
Course Description
This course is a detailed exploration of the timing and signal integrity analysis capabilities of the Tempus™ Timing Signoff Solution with Stylus Common UI. In this course, you analyze a design for static timing and signal integrity issues that are inherent in advanced process nodes with feature sizes 90nm and below. You also run signoff timing analysis to analyze timing issues on large designs and fix timing issues using the Innovus™ Implementation System with Stylus CUI.
Learning Objectives
After completing this course, you will be able to:
- Explore the features of the Tempus Stylus Common User Interface
- Identify timing analysis data requirements and import Single Corner designs and Multi-Mode Multi-Corner (MMMC) designs
- Identify and apply timing debug techniques using the Global Timing Debug interface
- Analyze a design for timing combined with signal integrity (SI)
- Compare parallel processing techniques such as Concurrent and Distributed MMMC
- Run ECO analysis and timing closure flow between the Stylus Innovus Implementation and the Stylus Tempus Signoff tools
Software Used in This Course
- Tempus Timing Signoff Solution with Stylus Common UI
- Innovus Implementation System with Stylus Common UI
Software Release(s)
SSV191, INNOVUS191
Modules in this Course
- Introduction to the Tempus Timing Signoff Solution with Stylus Common UI
- Design Import and Tool Flow
- Timing Analysis
- Timing Debug
- Crosstalk Analysis
- Parallel Processing
- Tempus ECO Flow
Audience
- Digital IC Designers
- IC Designers
- Place-and-Route Designers
Prerequisites
You must have an experience with or the knowledge of the following:
- Cadence®& physical design tools
- Static Timing Analysis
Related Courses
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