Length: 3 Days (24 hours)
Digital Badge Available
Course Description
Note: This course is based on the Stylus Common UI. Please consult with your design team or Cadence AE before deciding to take this course instead of the course called Innovus Implementation System (Block), which is based on the default UI. If there is not a clear preference, please select this course.
In this course, you learn how to use the Innovus™ Implementation System software using the Stylus Common User Interface (UI) to achieve the best power, performance and area (PPA) for your design. You learn several techniques for floorplanning and placement using the GigaPlace™ solver-based placement while implementing timing closure strategies with a multi-threaded, layer-aware timing and power-driven optimization engine to reduce dynamic and leakage power. You will learn how to set up and run the concurrent clock and datapath optimization engine to enhance cross-corner variability and boost performance with reduced power.
You run the slack-driven router with track-aware timing optimization, which enables you to achieve the multiple objectives that are a part of today's design requirements. You will learn how to diagnose and fix routing violations as well as explore challenges and solutions for design implementation in nodes that are 20nm and below.
Other topics in this course include using database access commands, wire editing, metal fill, ECOs and physical verification.
Learning Objectives
After completing this course, you will be able to:
- Import and floorplan your design
- Place the standard cells and blocks in the design
- Run power planning, power routing, and power analysis
- Reorder scan chains
- Analyze routing congestion
- Extract parasitics and generate timing reports
- Create clock trees
- Optimize and close timing
- Analyze how to optimize routing with technology (LEF) and design files
- Route critical nets with shielding and spacing
- Edit wires using the interactive wire editor
- Analyze and fix routing violations
- Report and fix timing and signal integrity violations
- Implement an Engineering Change Order (ECO)
- Explore the Foundation scripts to implement your design
- Explore the Stylus flow to implement your design
Software Used in This Course
- Digital Design Implementation System
The software includes Genus Synthesis Solution, Joules,and Innovus Implementation System.
Software Release(s)
DDI221
Modules in this Course
- Innovus Implementation System with Stylus Common UI Overview
- Design Import and Customizing the Innovus Implementation Environment
- Selecting and Highlighting Objects in the Design
- Floorplanning the Design
- Planning Power
- Routing Power with Special Route
- Running Placement Optimization
- Scan Optimization and Reordering
- Analyzing Route Feasibility with Early Global Router
- Multi-Mode Multi-Corner Analysis
- Extracting Parasitics and Running Timing Analysis
- Power, Performance, and Area Optimization
- Implementing the Clock Tree
- Detail Routing for Signal Integrity, Timing, Power and Design for Yield
- Wire Editing
- Preventing and Fixing Signal Integrity Problems
- Metal Fill
- Verification
- Engineering Change Orders
- Writing Out a Design
- Challenges of Advanced Nodes in Implementation
- Innovus Database Access Commands
- Stylus Flow Generation
Audience
- CAD Engineers
- Chip Designers
- Physical Layout Designers
Prerequisites
You must have experience with or knowledge of the following:
- Design methodology
Related Courses
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
