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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • Allegro X Design Platform
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
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      • AI IP Portfolio
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        • Arm-Based Solutions
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        • RF / Microwave
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        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
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        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
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        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
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        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
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        • RF / Microwave
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  • Genus Synthesis Solution with Stylus Common UI



Genus Synthesis Solution with Stylus Common UI

Online Courses
Instructor-Led Schedule
Date Version Country Location
18 - 20 Jul 2022 21.1 Germany Feldkirchen-Munich
Germany
ENROLL
03 - 05 Oct 2022 21.1 France Vélizy-Paris
France
ENROLL
17 - 19 Oct 2022 21.1 Germany Feldkirchen-Munich
Germany
ENROLL
08 - 10 Nov 2022 21.1 Israel Petah-Tikva-Tel Aviv
Israel
ENROLL
Scheduled upon demandOn demand EXPRESS INTERESTINQUIRE
Version Region
21.1 Online ENROLL
20.1 Online ENROLL
Other Versions Online EXPRESS INTERESTINQUIRE

Length: 3 days (24 Hours)

Digital Badge Available


Course Description

In this course, you learn about the features of the Cadence® Genus™ Synthesis Solution with Stylus Common UI with next generation synthesis capabilities (massively parallel, tight correlation, RTL design focus and Architecture-level PPA) and how SoC design productivity gap is filled by Genus. You learn several techniques to constrain designs, run static timing analysis, evaluate datapath logic, run physical synthesis, optimize for low-power structures, analyze DFT (design for testability) constraints, and interface with other tools in the Genus Stylus CUI. You will be able to identify the steps required to perform logic optimization for digital design and generate various input and output files.

You also learn how to run complete synthesis flow on a design with the given specifications and optimize it for area, timing, and power using the Stylus Common UI. You will learn to query the design database and set attributes for synthesis flow in the Genus Stylus CUI. You explore Multi-Mode Multi-Corner (MMMC) Synthesis Flow in Genus. You also identify Flowkit and Unified Metrics capabilities.

Learning Objectives

After completing this course, you will be able to:

  • Explore the features of the Genus Stylus Common User Interface
  • Apply the recommended synthesis flow using the Cadence Genus Synthesis Solution
  • Explore MMMC and how to set up and update the MMMC configuration of a design
  • Debug design scenarios
  • Use the extended datapath features
  • Optimize designs using the physical synthesis flow
  • Analyze and synthesize the design for low-power structures
  • Constrain the design for testability (DFT)
  • Identify the interface to Conformal® equivalence checker and other tools
  • Explore Flowkit and Unified Metrics

Software Used in This Course

  • Genus Synthesis Solution

Software Release(s)

Genus 21.1

Modules in this Course

  • Overview of Genus Synthesis Solution Stylus Common UI
  • Getting Started with Genus Synthesis Solution
  • Working in Genus Shell
  • Synthesis Flow in Genus
  • Finding Information in the Genus Design Hierarchy
  • Exploring Genus Stylus Common UI GUI (Optional)
  • Editing the Netlist
  • Reducing Runtime
  • Debugging Design Scenarios
  • Datapath Synthesis
  • Genus Physical Synthesis
  • Low-Power Optimization
  • Test Synthesis
  • Interfacing with LEC and Other Tools
  • FlowKit and Unified Metrics (Optional)

Audience

  • ASIC Designers
  • Digital IC Designers
  • Logic Designers

Prerequisites

You must have experience with or knowledge of the following:

  • Any HDL such as Verilog (recommended) or VHDL
  • Synthesis and ASIC design flow basics
  • Static Timing Analysis

Or you must have completed the following courses:

  • Basic Static Timing Analysis
  • Verilog Language and Application

Related Courses

  • Genus Synthesis Solution
  • Logic Equivalence Checking with Conformal EC
  • Innovus Digital Implementation (Block)
  • Innovus Digital Implementation (Hierarchical)


Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.

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Course ID: 86220

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