Genus Synthesis Solution with Stylus Common UI

Length: 2 days

Digital Badge Available

Course Description

In this course, you learn about the features of the Cadence^® Genus^™ Synthesis Solution with Stylus Common UIwith next generation synthesis capabilities (massively parallel, tight correlation, RTL design focus and Architecture-level PPA) and how SoC design productivity gap is filled by Genus. You learn several techniques to constrain designs, run static timing analysis, evaluate datapath logic, run physical synthesis, optimize for low-power structures, analyze DFT (design for testability) constraints, and interface with other tools in the Genus Stylus CUI. You will be able to identify the steps required to perform logic optimization for digital design and generate various input and output files.

You also learn how to run complete synthesis flow on a design with the given specifications and optimize it for area, timing, and power using theStylus Common UI. You will learn toquery the design database and set attributes for synthesis flow in the Genus Stylus CUI. You explore Multi Mode Multi Corner (MMMC) SynthesisFlow in Genus. You alsoidentify Flowkit and Unified Metrics capabilities.

Learning Objectives

After completing this course, you will be able to:

• Explore thefeatures of the GenusStylus Common User Interface
• Apply the recommended synthesis flow using the Cadence Genus Synthesis Solution
• Explore MMMC and how to set up and update the MMMC configuration of a design
• Debug design scenarios
• Use the extended datapath features
• Optimize designs using the physical synthesis flow
• Analyze and synthesize the design for low-power structures
• Constrain the design for testability (DFT)
• Identify the interface to Conformal^® equivalence checker and other tools
• Explore Flowkit and Unified Metrics

Software Used in This Course

• Genus Synthesis Solution

Software Release(s)

Genus 20.1

Modules in this Course

• Overview of Genus Synthesis Solution Stylus Common UI
• Getting Started with Genus Synthesis Solution
• Working in Genus Shell
• Synthesis Flow in Genus
• Finding Information in the Genus Design Hierarchy
• Exploring Genus Stylus Common UI GUI (Optional)
• Editing the Netlist
• Reducing Runtime
• Debug Design Scenarios
• Datapath Synthesis
• Genus Physical Synthesis
• Low-Power Optimization
• Test Synthesis
• Interfacing with LEC and Other Tools
• FlowKit andUnified Metrics (Optional)

Audience

• ASIC Designers
• Digital IC Designers
• Logic Designers

Prerequisites

You must have experience with or knowledge of the following:

• Any HDL such as Verilog (recommended) or VHDL
• Synthesis and ASIC design flow basics
• Static Timing Analysis

Or you must have completed the following courses:

• Basic Static Timing Analysis
• Verilog Language and Application

Related Courses

• Genus Synthesis Solution
• Logic Equivalence Checking with Conformal EC
• Innovus Digital Implementation (Block)
• Innovus Digital Implementation (Hierarchical)

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