Genus Synthesis Solution With Stylus Common UI

Learning Objectives

After completing this course, you will be able to:

• Explore the features of the Genus Stylus Common User Interface
• Apply the recommended synthesis flow using the Cadence Genus Synthesis Solution
• Explore MMMC and how to set up and update the MMMC configuration of a design
• Debug design scenarios
• Use the extended datapath features
• Optimize designs using the physical synthesis flow
• Analyze and synthesize the design for low-power structures
• Constrain the design for testability (DFT)
• Identify the interface to Conformal^® equivalence checker and other tools
• Explore Flowkit and Unified Metrics

Software Used in This Course

• Genus Synthesis Solution

Software Release(s)

Genus 19.1

Modules in this Course

• Overview of Genus Synthesis Solution Stylus Common UI
• Getting Started with Genus Synthesis Solution
• Working in Genus Shell
• Synthesis Flow in Genus
• Finding Information in the Genus Design Hierarchy
• Exploring Genus Stylus Common UI GUI (Optional)
• Editing the Netlist
• Reducing Runtime
• MMMC Flow
• Debug Design Scenarios
• Datapath Synthesis
• Genus Physical Synthesis
• Low-Power Optimization
• Test Synthesis
• Interfacing with LEC and Other Tools
• FlowKit and Unified Metrics (Optional)

Audience

• ASIC Designers
• Digital IC Designers
• Logic Designers

Prerequisites

You must have experience with or knowledge of the following:

• Any HDL such as Verilog (recommended) or VHDL
• Synthesis and ASIC design flow basics
• Static Timing Analysis

Or you must have completed the following courses:

• Basic Static Timing Analysis
• Verilog Language and Application

Related Courses

• Genus Synthesis Solution
• Logic Equivalence Checking with Conformal EC
• Innovus Digital Implementation (Block)
• Innovus Digital Implementation (Hierarchical)

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