Length: 2 Days (16 hours)
In this course, you are introduced to the new Cadence® third generation Xcelium™ simulator. You explore its Parallel Simulation features, how Xcelium is far more powerful than Incisive®, and the Incisive-to-Xcelium migration flow with an example demo video. You also learn about the multi-core capability of Xcelium with a demo video. All concepts are explained with the help of hands-on labs.
After completing this course, you will be able to:
- Perform simulation using the Cadence Xcelium simulator tool for design verification and debugging.
- Use the different commands of Xcelium simulator, starting with xrun with relevant options, to invoke the simulator, along with the SimVision™ tool GUI interface, for simulating and debugging any given design, in both Single-Core and Multi-Core modes.
Software Used in This Course
Modules in this Course
- Introduction to Xcelium Simulation
- The xrun Utility
- xrun Use Models
- Incisive to Xcelium Single-Core Migration
- The Xcelium Multi-Core Simulator
- The Xcelium and SimVision Interface
- Executing and Analyzing a Multi-Core Example with SimVision GUI and Indago Debug Analyzer
- SystemVerilog Support and Enhancement
- The Xcelium Textual Interface
- Debugging with SimVision and Textual/Batch Commands
- Latest Features and Updates
AudienceHardware, Software, Design or Verification Engineers who are familiar with SystemC, VHDL, and Verilog
You must have:
- Basic computer literacy: knowing how to use a shell and editor of your choice and navigate the file system
- A basic understanding of digital hardware design and verification
- Knowledge of a hardware description language to facilitate your learning experience