Perspec System Verifier – Basic

Length: 5 days (40 Hours)

Digital Badge Available

Course Description

This training course introduces to you the Cadence^® Perspec^™ System Verifier. The Perspec System Verifier is a software-driven system-on-chip (SoC) verification solution. The Perspec System Verifier improves SoC quality and saves time by reducing development effort for complex SoC-level use cases, creating coverage-driven automation of system use-case generation, and shrinking the time required to reproduce, debug, and fix complex SoC-level bugs.

Learning Objectives

After completing this course, you will be able to:

• Explain the Perspec System Verifier (SVR) purpose and usage
• Model components for the Perspec SVR
• Compose scenarios with the Perspec SVR
• Realize Perspec SVR scenario solutions in C
• Generate and examine coverage metrics from the Perspec SVR

Software Used in This Course

• Xcelium^™ Single-Core
• Perspec Composer/Solver
• Xcelium Perspec Runtime Option
• vManager^™ Linux Client

Software Release(s)

XCELIUM 1909

Modules in this Course

• Perspec System Verifier Introduction
• Perspec System Verifier Component Modeling Basics (3 parts)
• Perspec System Verifier Scenario Composition Basics (3 parts)
• Perspec System Verifier Test Realization Basics (3 parts)
• Perspec System Verifier Coverage Metrics Generation and Analysis

Audience

• SoC verification personnel new to the Perspec System Verifier

Prerequisites

You must have experience with or knowledge of the following:

• A high-level verification language
• System-level digital verification

Related Courses

• C++ Language Fundamentals for Design and Verification
• SystemVerilog for Design and Verification
• Xcelium Simulator

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