Length : 1 day
Course Description
In this course, you use the Cadence® Spectre® Accelerated Parallel Simulator (APS), which is a part of Virtuoso® Multi-Mode Simulation, to perform advanced SPICE-accurate simulation for faster convergence on design goals while offering scalable performance and capacity over the baseline Spectre Classic Simulator. You examine how the proprietary full-matrix solving technology in Spectre Accelerated Parallel Simulator delivers unparalleled scalability and multithreading capability using modern multi-core computing platforms.
You then verify the circuit performance and identify the potential failure modes using the Checks/Asserts feature of Virtuoso ADE Explorer with APS.
You also learn how to perform post-layout simulation with Spectre APS. You identify stitching of parasitics (DSPF, SPEF, and DPF files) and inclusion of parasitic files for post-layout simulation. Finally, you enable post-layout optimization (+postlayout) to perform parasitic reduction.
Learning Objectives
After completing this course, you will be able to:
- Use the Spectre Accelerated Parallel Simulator (APS) modes (+aps) and (++aps) to run high performance simulation
- Debug performance or convergence-related simulation issues using the Spectre Diagnose Mode (+diagnose)
- Create circuit checks and device checks (Spectre assert statements) from the Checks/Asserts assistant
- Use the Virtuoso ADE Explorer to verify circuit performance and identify potential failures
- Enable post-layout optimization (+post layout) to perform parasitic reduction
- Run a post-layout simulation using dspf_include and stitching methodologies
Software Used in This Course
- Spectre Classic Simulator
- Spectre Accelerated Parallel Simulator (APS)
- Spectre Multimode Simulation
- Spectre Power Option
- Cadence Design Framework II
- Virtuoso Schematic Editor
- Virtuoso Layout Suite
- Virtuoso ADE Explorer
- Virtuoso Visualization and Analysis XL
Software Release(s)
SPECTRE19.1(ISR2), IC6.1.8(ISR8)
Modules in this Course
- Spectre APS Technology
- Design Checks with Spectre APS
- Post-Layout Simulation with Spectre APS
Audience
- IC Designers
- RF Designers
- Electrical Engineers
- Design Engineers
- Chip Designers
- Analog and Mixed-Signal Designers
Prerequisites
You must have:
- The ability to create schematics and run simulations with Cadence tools
- A working knowledge of simulation techniques with different netlist formats
Or you must have completed the following courses:
Related Courses
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
Free Online Training Bytes (Videos)
Course ID: 86195
