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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
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          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
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          • Spectre FX Simulator
          • Virtuoso Layout Suite
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          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
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          • Computational Fluid Dynamics
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          • Clarity 3D Transient Solver
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          • AWR Free Trial
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          • Augmented Reality Lab Tools
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  • Variation Analysis Using the Virtuoso Variation Option



Variation Analysis Using the Virtuoso Variation Option

Instructor-Led Schedule
Date Version Country Location
Scheduled upon demandOn demand EXPRESS INTERESTINQUIRE

Length: 1 day (8 Hours)

Course Description

In this course, you use the Virtuoso Variation Option available in IC 617 along with the Virtuoso ADE Assembler maestro tool to set up and run advanced statistical analysis on designs. You analyze yield and identify the mismatch contribution of your devices to see which results need improvement. You use Monte Carlo techniques such as sample reordering to estimate the yield without using a large number of samples and then use this information and create statistical corners to analyze statistical variation in the circuit and decrease its impact on the yield. Advanced corner creation methods are discussed. These can aid in manual tuning and application of optimization techniques on your design. High-yield sampling methods are employed to estimate the yield of high sigma designs. The Improve Yield run mode in the ADE Assembler is also discussed.

Learning Objectives

After completing this course, you will be able to:

  • Set up and run a Monte Carlo analysis
  • Determine the yield after a Monte Carlo run
  • Print statistical parameters and plot histograms
  • Post-process Monte Carlo results and create statistical corners that can be in future simulations used to tune or optimize your design
  • Use the Virtuoso Variation Option license to run advanced options of the Monte Carlo run mode
  • Analyze device contribution to mismatch using the Sensitivity Accuracy method
  • Run yield verification using the reorder samples method
  • Estimate high yield in designs using advanced statistical methods
  • Create high-sigma (>3) statistical corners using advanced sampling methods
  • Use the Improve Yield run mode to improve your design yield

Software Used in This Course

  • Virtuoso ADE Assembler
  • Virtuoso Variation Option
  • Spectre Circuit Simulator

Software Release(s)

IC 6.1.7 ISR8, Spectre 16.1

Modules in this Course

  • The Virtuoso Design Environment (Optional)
  • Monte Carlo Simulations in the Virtuoso ADE Assembler
  • Advanced Statistical Analysis Using the Virtuoso Variation Option License
  • Improve Yield for a Design

Audience

  • Analog/Mixed-Signal Design Engineers

Prerequisites

You must have experience with or knowledge of the following:

  • Statistical analysis concepts
  • Virtuoso ADE Assembler Environment
  • Spectre Circuit Simulator

Or you must have completed the following course:

  • Virtuoso ADE Assembler S1: Introducing the Assembler Environment

Related Courses

  • Virtuoso ADE Assembler S1: Introducing the Assembler Environment
  • Virtuoso ADE Assembler S3: Circuit Checks, Device Asserts, and Reliability Analysis
  • Virtuoso ADE Explorer S1: Set Up and Run Analog Simulations Using the Spectre Simulator
  • Virtuoso ADE Explorer S2: Analyzing Simulations Using the ViVA XL Waveform Tool
  • Virtuoso ADE Explorer S3: Corner Analysis and Monte Carlo Simulations
  • Virtuoso ADE Explorer S4: Real-Time Tuning, Checks/Asserts, and Reliability Analysis
  • Virtuoso ADE Verifier

Click here to view course learning maps, and here for complete course catalogs.

Course ID: 86188

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