Low-Power Synthesis Flow with Genus Synthesis Solution

This is an Engineer Explorer course for designers familiar with synthesis using the Genus^™ Synthesis Solution.

In this course, you explore and implement several low-power techniques to reduce both dynamic and leakage power during synthesis. You use multiple supply voltage (MSV) design, power shutoff (PSO) synthesis and dynamic voltage frequency scaling (DVFS) synthesis. You run low-power flow using CPF and IEEE 1801 and troubleshoot a low-power design. You apply formal verification to validate your power constraints and ensure the functionality of a low-power design.

Here is the sample video from the course.

Note: This course is based on the legacy user interface and not the common user interface.

• Genus Synthesis Solution

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