Length : 2 days
In this course, you learn to use Genus™ Synthesis Solution to insert test structures in your design. You learn how to set up constrains for DFT, checking DFT rules, fixing violations, synthesizing the design, and configuring and connecting scan chains. You learn to generate various reports and to interface with other tools. You also learn Hierarchical Scan Synthesis and Advanced DFT logic insertion like PMBIST, Compression, LBIST, OPCG etc., in design.
Note: This course is based on the legacy user interface and not the common user interface.
After completing this course, you will be able to:Constrain the design for testability (DFT)Run DFT rule checker and fix DFT violationsSynthesize the design and map to scanSet up DFT configuration constraints and preview scan chainsConnect scan chainsRun hierarchical scan insertionRun advanced testability features, boundary scan, PMBIST, Compression and OPCG
Software Used in This Course
Genus Synthesis Solution
Modules in this CourseIntroduction to DFT FeaturesTest Synthesis Flow in Genus Synthesis SolutionHierarchical Scan SynthesisAdvanced Testability Features
- Design Engineers
- Design for Testability Engineers
- Digital IC Designers
You must have:
- Experience with Genus Synthesis Solution
Or you must have completed the following course: