Advanced Synthesis with Genus Synthesis Solution

After completing this course, you will be able to:

• Identify the features of the Cadence^® Genus Synthesis Solution
• Analyze the log file to debug and fix the timing of a design
• Apply retiming to fix the timing of a complex block
• Identify best practices for synthesizing complex designs
• Learn how to use Genus Physical
• Analyze Physical Synthesis results
• Identify multimode design methodology
• Verify designs using Conformal^® Equivalence Checker
• Validate constraints using Conformal Constraint Designer
• Set up power intent based Low-Power Flow in Genus

• Overview of Genus Synthesis Solution
• Analyzing Results
• Optimizing Datapaths
• Optimization Best Practices
• Genus Physical Synthesis
• Debugging Problems in Genus Physical
• Multiple Mode Designs
• Genus-LEC Verification Flow
• Low-Power Synthesis in Genus

• ASIC Designers
• Digital IC Designers
• Logic Designers

You must have experience with the following:

• Genus Synthesis Solution

Or you must have completed the following course:

• Genus Synthesis Solution

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.