Length : 1/2 day
For classroom delivery, this course is taught as half day session (4 hours).
This is a lecture-only class.
In this course, you analyze and debug the layout issues which you come across in your layout design tasks.
- Analyze why Technology Libraries are not visible in Library Manager even though they are defined in the cds.lib file and fix the issues.
- Debug why few Toolbar Icons are not visible to use in the layout canvas and fix the issues.
- Explore why Partial Selection fails when stretching wires using Partial Select and Quick Align and fix the issues.
- Explore why Auto Via Creation with Check Shape Connectivity option fails and fix the issues.
- Analyze why the Mark Net command creates false shorts and explore how to fix the issues.
- Analyze why Remaster Instances command fails with few abstract views not updated to layout views and fix the issues.
- Analyze why Chaining and Folding of transistors fail when running Generate All From Source (GFS) and Generate Selected From Source (GSFS) commands and fix the issues.
- Analyze why Oxide rectangle over the pcell introduces a short and fix the issues.
This course is part of a series; the other courses in the series are:
After completing this course, you will be able to:
- Analyze and debug the layout issues in your layout design tasks.
Software Used in This Course
- Virtuoso Layout Suite L/XL
- IC 6.1.6
Day 1 (This is a ½-day course)
- Debugging Issues in Viewing Libraries in Library Manager
- Debugging Issues in Viewing Toolbar Icons with Toolbar Manager
- Debugging Issues in Using Quick Align Command
- Debugging Issues in Using Create Via Command with Check Shape Connectivity Option
- How to Use Via Layers in Mark Net Command to Avoid Reporting False Shorts
- Debugging Issues in Using Remaster Instances Command
- How to Enable Chaining and Folding of Transistors when Running Generate All From Source (GFS) and Generate Selected From Source (GSFS) Commands
- How Valid Layers are Interpreted by Virtuoso LS-XL and How to Remove the Shorts Created by Valid Layers
- Layout Design Engineers
- Layout CAD Managers
You must have:
- Experience with the connectivity-driven layout flow.
- Knowledge of schematic symbols and MOS devices.
- Basic knowledge of UNIX/Linux.
Or you must have completed the following courses: