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- Fundamentals of IEEE 1801 Low-Power Specification Format
Fundamentals of IEEE 1801 Low-Power Specification Format
Date | Version | Country | Location | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
Version | Region | |
---|---|---|
4.0 | North America | ENROLL |
3.0 | North America | ENROLL |
2.0 | North America | ENROLL |
Other Regions | EXPRESS INTERESTINQUIRE |
Length : 1 day
Course Description
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This is an Engineer Explorer course for ASIC designers familiar with Low Power technology.
This one-day course is a complete tutorial for understanding the fundamentals of IEEE 1801 low power specification format concepts. You learn about IEEE 1801 power supply networks, ground ports and nets, creating and connecting supply ports/nets, power domain, power switch, power states, defining isolation and level shifter strategies, hierarchical UPF and various versions of UPF. You also explore how power intent information can be used for a design across various stages of flow such as functional verification, synthesis, logic equivalency checking, place and route, test, timing signoff, power integrity and so forth using Cadence® tools.
Learning Objectives
After completing this course, you will learn:
- Concepts of Low Power
- Evolution of IEEE 1801
- Explore IEEE 1801 Concepts
- Identify Power Supply Network (PSN), Power State, Power Domain Interface
- Write IEEE 1801 for MSV/PSO Design
- Understand Retention, Isolation and Level Shifter Strategy
- Implement Power Switch
- Explore Low Power Strategies
- Concept of Hierarchical UPF
- Types of Hierarchical UPF
- Dealing with Three Versions of UPF
- Debug Design Scenarios
- Analyze Non-Standard IEEE 1801 Coding Styles
- Explore Cadence Tools Supporting IEEE 1801
- Set Up and Run IEEE 1801 Flow for Cadence Tools
Software Used in This Course
- Conformal Low Power Verify
Software Release(s)
CONFRML182
Modules in this Course
- Low Power Concepts
- IEEE 1801 Introduction
- IEEE 1801 Basic Concepts
- Examples of IEEE 1801 Format for MSV/PSO Design
- Low Power Strategies
- Hierarchical UPF
- Dealing with Three Versions of UPF
- Debugging Design Scenarios
- Non-Standard IEEE 1801 Coding
- Cadence Tools Flow and Setup for IEEE 1801
Audience
- Verification Engineers
- Place and Route Designers
- IC Designers
- Hardware Engineers
- Electrical Engineers
- ASIC Designers
- Design Engineers
- Circuit Designers
- Chip Designers
Prerequisites
You must have experience with or knowledge of the following:
- HDL
- Logic Design
- Basics of ASIC design
Related Courses
- Low-Power Simulation with IEEE Std 1801 UPF
- Low-Power Flow with Innovus Implementation System
- Low-Power Synthesis Flow with Genus™ Stylus Common UI
- Conformal Low-Power Verification
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
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