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- Fundamentals of IEEE 1801 Low-Power Specification Format
Fundamentals of IEEE 1801 Low-Power Specification Format
Date | Version | Country | Location | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
Version | Region | |
---|---|---|
6.0 | Online | ENROLL |
5.0 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length: 1 day
Digital Badge Available
Course Description
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This is an Engineer Explorer course for ASIC designers familiar with low-power technology.
This one-day course is a complete tutorial for understanding the fundamentals of IEEE 1801 low-power specification format concepts. You learn about IEEE 1801 power supply networks, ground ports and nets, creating and connecting supply ports/nets, power domain, power switch, power states, defining isolation and level shifter strategies, hierarchical UPF and various versions of UPF. You also explore how power intent information can be used for a design across various stages of flow such as functional verification, synthesis, logic equivalency checking, place-and-route, test, timing signoff, power integrity and so forth using Cadence® tools.
Learning Objectives
After completing this course, you will learn:
- Concepts of low power
- Evolution of IEEE 1801
- Explore IEEE 1801 concepts
- Identify Power Supply Network (PSN), power state, power domain interface
- Write IEEE 1801 for MSV/PSO design
- Understand retention, isolation and level shifter strategy
- Implement power switch
- Explore low-power strategies
- Concept of hierarchical UPF
- Types of hierarchical UPF
- Dealing with the three versions of UPF
- Debug design scenarios
- Analyze non-standard IEEE 1801 coding styles
- Explore Cadence tools supporting IEEE 1801
- Set up and run IEEE 1801 flow for Cadence tools
Software Used in This Course
- Conformal Low Power Verify
Software Release(s)
CONFRML 202
Modules in this Course
- Low-Power Concepts
- IEEE 1801 Introduction
- IEEE 1801 Basic Concepts
- Examples of IEEE 1801 Format for MSV/PSO Design
- Low-Power Strategies
- Hierarchical UPF
- Dealing with Three Versions of UPF
- Debugging Design Scenarios
- Non-Standard IEEE 1801 Coding
- Cadence Tools Flow and Setup for IEEE 1801
Audience
- Verification Engineers
- Place and Route Designers
- IC Designers
- Hardware Engineers
- Electrical Engineers
- ASIC Designers
- Design Engineers
- Circuit Designers
- Chip Designers
Prerequisites
You must have experience with or knowledge of the following:
- HDL
- Logic design
- Basics of ASIC design
Related Courses
- Low-Power Simulation with IEEE Std 1801 UPF
- Low-Power Flow with Innovus Implementation System
- Low-Power Synthesis Flow with Genus Stylus Common UI
- Conformal Low-Power Verification
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
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