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- Quantus Transistor-Level T3: Extracted View Flows and Advanced Features
Quantus Transistor-Level T3: Extracted View Flows and Advanced Features
Date | Version | Country | Location | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
Version | Region | |
---|---|---|
21.2 | Online | ENROLL |
21.1 | Online | ENROLL |
19.1 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length: ½ Days (4 Hours)
Digital Badge Available
Course Description
Quantus Extraction Solution – RLCK Extraction You TrustFor classroom delivery, this course is taught as a half-day session (4 hours). The course is designed to offer a user-level experience on the next generation parasitic extraction solution from the Cadence®-Quantus™ Extraction Solution. You start with exploring the advanced node design solutions in Quantus. You will analyze extraction challenges in FinFETs, 3DIC and Double/Multiple Patterning (DPT/MPT) designs and respective Quantus Extraction Solutions. You will also check the pros and cons of colored and colorless extraction flows with pessimism reduction. You will then perform the Quantus-based 7nm DPT Modeling, Shift Corners flows and explore 3D-IC Designs with TSV and Micro-Bumps. Finally, you will review the transistor-level EMIR Analysis flow with the Voltus™-Fi Custom Power Integrity Solution and its advanced features. The Quantus Extraction Solution is integrated into the Virtuoso® environment for easy access.
NOTE: This course is compatible with IC 6.1.8 and ICADVM 20.1. Lab session is available for this course.
Learning Objectives
After completing this course, you will be able to:
- Discuss the advanced node (FinFET & DPT) design and extraction challenges
- Check how Quantus addresses advanced node extraction challenges
- Explore the Fin shapes formation and layer mapping with Quantus
- Analyze diffusion stretching and ICT file syntax for the FinFET process
- Explore the fully colored design flow – emphasis on MPT, decomposition and pessimism reduction
- Check the Quantus-based 7nm DPT Modeling and Shift Corners flows
- Examine Quantus support for the HPB Airgap Dielectrics
- Explore Quantus-based extraction flows for 3D-IC designs with TSV and Micro-Bumps
- Evaluate comprehensive Quantus integration to the Virtuoso platform
- Review the transistor-level EMIR Analysis flow with the Voltus-Fi Custom Power Integrity Solution
- Explore the advanced features in Voltus-Fi-L
Software Used in This Course
- Virtuoso Layout Suite
- Pegasus™ Verification System
- Quantus Extraction Solution
- Voltus-Fi Custom Power Integrity Solution
- Spectre Accelerated Parallel Simulator
Software Release(s)
QUANTUS 21.2, PEGASUS 21.3, IC 6.1.8, ICADVM 20.1, SPECTRE 21.1.1
Modules in this Course
- Quantus Advanced Node Features
- Post-Layout Simulation and EMIR Analysis with Voltus-Fi-L
Audience
- Physical Verification and Extraction engineers who need to address parasitic issues in their advanced node designs
Prerequisites
You must have:
- Knowledge and experience with physical design, verification and extraction
- Familiarity with the Virtuoso Layout Suite
- Familiarity with basic concepts of design parasitics, EMIR effects and simulation
Related Courses
- Quantus Transistor-Level T1: Overview and Technology Setup
- Quantus Transistor-Level T2: Parasitic Extraction
- Virtuoso Layout Design Basics
- Physical Verification System
- Pegasus Verification System
- Virtuoso Analog Design Environment
- Spectre Accelerated Parallel Simulator
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
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