Length : 1/2 day
Digital Badge Available:
Course Description
Quantus Extraction Solution – RLCK Extraction You Trust
For classroom delivery, this course is taught as a half-day session (4 hours).
This is a lecture-only class.
The course is designed to offer user-level experience on the next generation parasitic extraction solution from the Cadence®–Quantus™ Extraction Solution. You start with exploring the advanced node design solutions in Quantus. You will analyze extraction challenges in FinFETs, 3D-IC and Double/Multiple Patterning (DPT/MPT) designs and respective Quantus Extraction Solutions. You will also check the pros and cons of colored and colorless extraction flows with pessimism reduction. You will then perform Quantus-based 7nm DPT Modeling, Shift Corners flows and explore 3D-IC Designs with TSV and Micro-Bumps. Finally, you will review the Transistor-Level EMIR Analysis flow with Voltus™-Fi Custom Power Integrity Solution and its advanced features. The Quantus Extraction Solution is integrated to the Virtuoso® environment for easy access.
Learning Objectives
After completing this course, you will be able to:
- Discuss Advanced Node (FinFET & DPT) Design and Extraction challenges
- Check how Quantus addresses Advanced node Extraction challenges
- Explore Fin Shapes Formation and Layer Mapping with Quantus
- Analyze Diffusion Stretching and ICT File syntax for the FinFET process
- Explore the Fully Colored Design flow – emphasis on MPT, Decomposition and Pessimism Reduction
- Check the Quantus-based 7nm DPT Modeling and Shift Corners flows
- Examine Quantus support for HPB Airgap Dielectrics
- Explore Quantus-based extraction flows for 3D-IC Designs with TSV and Micro-Bumps
- Evaluate Comprehensive Quantus Integration to the Virtuoso platform
- Review the Transistor-Level EMIR Analysis flow with Voltus-Fi Custom Power Integrity Solution
- Explore the advanced features in Voltus-Fi-XL
Software Used in This Course
- Virtuoso Layout Suite
- Pegasus™ Verification System
- Quantus Extraction Solution
- Voltus-Fi Custom Power Integrity Solution
Software Release(s)
EXT191, PEGASUS191, IC618
Modules in this Course
- Quantus Advanced Node Features
- Post-Layout Simulation and EMIR Analysis with Voltus-Fi-XL
Audience
- Physical Verification and Extraction engineers who need to address parasitic issues in their advanced node designs
Prerequisites
You must have:
- Knowledge and experience with physical design, verification and extraction
- Familiarity with the Virtuoso Layout Suite
- Familiarity with basic concepts of design parasitics, EMIR effects and simulation
Related Courses
- Quantus Transistor-Level T1: Overview and Technology Setup
- Quantus Transistor-Level T2: Parasitic Extraction
- Virtuoso Layout Design Basics
- Physical Verification System
- Assura® Parasitic Extraction (RCX)
- Cadence QRC Techgen Developer
- Virtuoso Analog Design Environment
- High-Performance Simulation Using Spectre® Simulators
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
INSTRUCTIONAL VIDEOS
Training Bytes
Log into Cadence Online Support to watch our short videos to explore an element of a language, make sense of a methodology, or learn how to do a task
SELF PACED ONLINE TRAINING
Online Training Subscription
Multiple online courses of one or more technology groups, for 12 months unlimited, per student