Quantus Transistor-Level T2: Parasitic Extraction

Length: 1 Day (8 Hours)

Digital Badge Available

Course Description

For classroom delivery, this course is taught as a full-day session (8 hours).The course is designed to offer user-level experience on the next generation parasitic extraction solution from the Cadence^®–Quantus™ Extraction Solution. You start with an overview of the Pegasus-Quantus data flow and advance to hands-on extraction activities. You then set up the extraction environment in GUI mode or the command line. You explore the considerations, settings and various features for the Quantus Extraction Solution such as random walk field solver, adaptive meshing, split wide MOS or hierarchical extraction and then run multi-corner extraction with Quantus and perform Reduction Control and Advanced Virtual Metal Fill (VMF). Under specific extraction capabilities, you check the parasitic inductance extraction with PEEC – Wide Band Models and parasitic substrate extraction with Substrate Noise Analysis (SNA).In this course, you use the Virtuoso^® Layout Suite. The Quantus Extraction Solution is integrated into the Virtuoso menu bar for easy access. 

NOTE: This course is compatible with IC 6.1.8. and ICADVM 20.1. A lab session is added for this course.

Learning Objectives

After completing this course, you will be able to:

• Decode the transistor-level Pegasus-Quantus user flow
• Perform the Quantus Extraction in Batch and GUI modes
• Extract Parasitic Capacitance, Resistance, Inductance and Substrate
• Set up Quantus Extraction Run form: Tabs/Features/Options
• Set up and run Quantus in FS mode, Resistance Mesh Extraction, and Parasitic Cell Blocking
• Derive the PowerMOS characterization and verification
• Set up and run Hierarchical Extraction, Macro Cells Extraction, Substrate RC Reduction
• Perform the Multi-Corner Extraction with Quantus
• Close ECOs with the Quantus Automatic Incremental Extraction flow
• Conduct Inductance Extraction in PEEC and Ladder Network models
• Elicit Substrate Extraction and Analysis flows 
• Run parasitic substrate extraction with the Substrate Noise Analysis (SNA)

Software Used in This Course

• Quantus Extraction Solution
• Pegasus^™ Verification System
• Virtuoso Layout Suite

Software Release(s)

QUANTUS 21.2, PEGASUS 21.3, IC 6.1.8, ICADVM 20.1

Modules in this Course

• Overview of Quantus (Pegasus) Parasitic Extraction
• Quantus Parasitic RC Extraction
• Quantus Parasitic Inductance Extraction
• Quantus Parasitic Substrate Extraction
• Common Command Language (CCL)

Audience

• Physical Verification and Extraction Designers who need to address parasitic issues in their design

Prerequisites

You must have:

• Knowledge and experience with physical design, verification and extraction
• Familiarity with the Virtuoso Layout Suite
• Familiarity with basic concepts of design parasitics, EMIR effects and simulation

Related Courses

• Quantus Transistor-Level T1: Overview and Technology Setup
• Quantus Transistor-Level T3: Extracted View Flows and Advanced Features
• Virtuoso Layout Design Basics
• Physical Verification System
• Pegasus Verification System
  
• Virtuoso Analog Design Environment
• Spectre Accelerated Parallel Simulator

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