Quantus Transistor-Level T2: Parasitic Extraction

Length : 1 day

Digital Badge Available

Course Description

Quantus Extraction Solution - RLCK Extraction You Trust

For classroom delivery, this course is taught as a full-day session (8 hours).

 The course is designed to offer user-level experience on the next generation parasitic extraction solution from Cadence^®–Quantus^™ Extraction Solution. You start with an overview of the Pegasus–Quantus data flow and advance to hands-on extraction activities. You then set up the extraction environment in GUI mode or the command line. You explore the considerations, settings and various features for Quantus Extraction Solution such as random walk field solver, adaptive meshing, split wide MOS or hierarchical extraction and then run multi-corner extraction with Quantus and perform Reduction Control & Advanced Virtual Metal Fill (VMF). Under specific extraction capabilities, you check the parasitic inductance extraction with PEEC – Wide Band Models and parasitic substrate extraction with Substrate Noise Analysis (SNA). In this course, you use the Virtuoso^® Layout Suite. The Quantus Extraction Solution is integrated to the Virtuoso menu bar for easy access.

Learning Objectives

After completing this course, you will be able to:

• Decode transistor-level Pegasus–Quantus user flow
• Perform Quantus extraction in Batch and GUI modes
• Explore Parasitic Capacitance, Resistance, Inductance and Substrate extraction
• Check the Quantus RLCK Extraction Run Form – Tabs/Features/Options
• Explore features such as Quantus FS, Resistance Mesh, Parasitic Cell Blocking
• Derive PowerMOS characterization and verification
• Learn Hierarchical Extraction, Macro Cells Extraction, Substrate RC Reduction
• Perform multi-corner extraction with Quantus
• Close ECOs with Quantus Automatic Incremental Extraction flow
• Conduct Inductance Extraction in PEEC and Ladder Network models
• Elicit Substrate extraction and Analysis flows
• Run parasitic substrate extraction with Substrate Noise Analysis (SNA)

Software Used in This Course

• Quantus Extraction Solution
• Pegasus^™ Verification System
• Virtuoso Layout Suite

Software Release(s)

EXT191, PEGASUS191, IC618

Modules in this Course

• Overview Of Quantus (Pegasus) Parasitic Extraction
• Quantus Parasitic RC Extraction
• Quantus Parasitic Inductance Extraction
• Quantus Parasitic Substrate Extraction

Audience

• Physical Verification and Extraction Designers who need to address parasitic issues in their design

Prerequisites

You must have:

• Knowledge and experience with physical design, verification and extraction
• Familiarity with the Virtuoso Layout Suite
• Familiarity with basic concepts of design parasitics, EMIR effects and simulation

Related Courses

• Quantus Transistor-Level T1: Overview and Technology Setup
• Quantus Transistor-Level T3: Extracted View Flows and Advanced Features
• Virtuoso Layout Design Basics
• Physical Verification System
• Assura Parasitic Extraction (RCX)
• Cadence QRC Techgen Developer
• Virtuoso Analog Design Environment
• High-Performance Simulation Using Spectre^® Simulators

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.