Low-Power Flow with Innovus Implementation System

Length : 1 day

Course Description

In this course, you explore and implement several low-power techniques to reduce both dynamic and leakage power during synthesis and design implementation. You run formal verification to ensure the functionality of a low-power design.

Learning Objectives

After completing this course, you will be able to:

• Implement Multi-Supply Multi-Voltage (MSMV) regions to reduce power consumption
• Implement a low-power clock tree
• Run concurrent timing, MSV optimization, and multi-VT (leakage) optimization
• Implement MSMV-aware detail routing
• Analyze data and debug power problems at different stages of the flow

Software Used in This Course

• Conformal^® Low Power
• Innovus^™ Implementation System
• Voltus^™ IC Power Integrity Solution
• Tempus^™ Timing Signoff Solution

Software Release(s)

INNOVUS191, SSV191, CONFRML192

Modules in this Course

• Power Reduction
• Implementing Low-Power Using Innovus Technology
• Multi-Mode Multi-Corner Settings for Design Import
• Creating Physical Power Domain
• Level-Shifter and Isolation Cells
• Power Shutoff Domain Implementation
• Power Planning and Power Routing
• Leakage and Dynamic Power Optimization
• Power-Domain-Aware Routing
• Debugging a Low-Power Design
• Low-Power Foundation Flow
• Signoff Considerations for Low-Power Designs

Audience

• ASIC Designers
• Chip Designers
• Digital IC Designers

Prerequisites

You must have experience with or knowledge of the following:

• Design methodology
• Place and route

Related Courses

• Innovus Implementation System (Block)
• Innovus Implementation System (Hierarchical)
• Fundamentals of IEEE 1801 Low-Power Specification Format

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