Length : 1 day
Course Description
In this course, you explore and implement several low-power techniques to reduce both dynamic and leakage power during synthesis and design implementation. You run formal verification to ensure the functionality of a low-power design.
Learning Objectives
After completing this course, you will be able to:
- Implement multi-supply multi-voltage (MSMV) regions to reduce power consumption
- Implement a low-power clock tree
- Run concurrent timing, MSV optimization, and multi-VT (leakage) optimization
- Implement MSMV-aware detail routing
- Analyze data and debug power problems at different stages of the flow
Software Used in This Course
- Conformal® Low Power
- Innovus™ Implementation System
- Voltus™ IC Power Integrity Solution
- Tempus™ Timing Signoff Solution
Software Release(s)
INNOVUS181, SSV181, CONFRML182
Modules in this Course
- Power Reduction
- mplementing Low-Power Using Innovus Technology
- Multi-Mode Multi-Corner Settings for Design Import
- Creating Physical Power Domain
- Level-Shifter and Isolation Cells
- Power Shutoff Domain Implementation
- Power Planning and Power Routing
- Leakage and Dynamic Power Optimization
- Power-Domain-Aware Routing
- Debugging a Low-Power Design
- Low-Power Foundation Flow
- Signoff Considerations for Low-Power Designs
Audience
- ASIC Designers
- Chip Designers
- Digital IC Designers
Prerequisites
You must have experience with or knowledge of the following:
- Design methodology
- Place and route
Related Courses
Click here to view course learning maps, and here for complete course catalogs.
