Low-Power Flow with Innovus Implementation System

Length: 1 day (8 hours)

Digital Badge Available

Course Description

This is an Engineer Explorer course for designers familiar with synthesis concepts.

In this course, you analyze and implement several low-power techniques to reduce both dynamic and leakage power during synthesis and design implementation. You run formal verification to ensure the functionality of a low-power design.

Learning Objectives

After completing this course, you will be able to:

• Implement low-power design techniques using Innovus Implementation System software
• Analyze Multi-Supply Multi-Voltage (MSMV) regions to reduce power consumption
• Run concurrent timing, MSV optimization, and multi-VT (leakage) optimization
• Implement MSMV-aware detail routing
• Analyze data and debug power problems at different stages of the flow

Software Used in This Course

• Innovus^™ Implementation System
• Conformal® Low Power

Software Release(s)

INNOVUS211, CONFRML211

Modules in this Course

• Introduction to Low-Power Designs
• Power Reduction
• Implementing Low-Power Using Innovus Technology
• Floorplanning and Placement of Low-Power Cells
• Power Planning and Power Routing
• Leakage and Dynamic Power Optimization
• Power-Domain-Aware Routing
• Signoff Considerations for Low-Power Designs
• Verifying a Low-Power Design

Audience

• ASIC Designers
• Chip Designers
• Digital IC Designers

Prerequisites

You need to have already taken the following course or have experience with the software:

• Innovus Implementation System (Block) 
• Innovus Implementation System software
• Fundamentals of IEEE 1801 Low-Power Specification Format

Related Courses

• Innovus Implementation System (Block)
• Innovus Implementation System (Hierarchical)
• Fundamentals of IEEE 1801 Low-Power Specification Format

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