Length : 1 day
Digital Badge Available
Course Description
In this course, you explore the features of the Innovus® Implementation System for creating and implementing a hierarchical design. You learn several techniques to floorplan your design, create partitions (hierarchical blocks), run place and route, and optimize the design (at the block level and top level) to close timing. You learn techniques to reduce the memory size and run time by using interface logic models (ILMs).
Learning Objectives
After completing this course, you will be able to:
- Floorplan and create partitions for your design
- Implement the blocks and the top-level design using various methods after analyzing the benefits and drawbacks of each method
Software Used in This Course
Innovus Implementation System
Software Release(s)
INNOVUS201
Modules in this Course
- Innovus Implementation System Overview
- Partitioning the Design
- Placing Pins
- Bus Planning
- Interface Logic Models (ILMs)
Audience
- ASIC Designers
- CAD Engineers
- Chip Designers
- Layout Designers
Prerequisites
You must have experience with or knowledge of:
- Design methodology
- Place and route
Related Courses
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
INSTRUCTIONAL VIDEOS
Training Bytes
Log into Cadence Online Support to watch our short videos to explore an element of a language, make sense of a methodology, or learn how to do a task
“Everything was perfect. I'm very delighted I took part in it, it's incredibly useful to have a basic understanding of the whole flow (…).Lots of useful suggestions for further projects in regards of software questions. Very well described lab manual.”
“In general, I can fully recommend this training(...)we learned a lot. The questions we had, were answered. Issues(...)during the labs had been solved/explained. The presentation style is interactive and animates one to follow the content.”