Innovus Implementation System (Block)

Learning Objectives

After completing this course, you will be able to:

• Import and floorplan a design
• Run placement and optimization using GigaPlace technology
• Plan, route and analyze the power
• Run timing analysis and debug results
• Create clock trees and concurrently run datapath optimization
• Run optimization for power, performance and area
• Run the slack-driven router with track-aware timing optimization
• Run global and detail routing for timing and signal integrity
• Debug routing violations
• Create and edit wires interactively
• Run ECOs on a design
• Address 20nm (and below) challenges as a result of Multi-Pattern Technology (MPT)
• Run design verification for geometry, connectivity, antenna and metal fill
• Run database access commands
• Run Foundation Flow scripts

Software Used in This Course

• Innovus Implementation System

Software Release(s)

INNOVUS191

Modules in this Course

• Innovus Implementation System Overview
• Design Import and Customizing the Innovus Implementation System Environment
• Selecting and Highlighting Objects in the Design
• Floorplanning the Design
• Planning Power
• Routing Power with Special Route
• Running Placement Optimization
• Scan Optimization and Reordering
• Analyzing Route Feasibility with Early Global Route
• Multi-Mode Multi-Corner Analysis
• Extracting Parasitics and Running Timing Analysis
• Power, Performance and Area Optimization
• Implementing the Clock Tree
• Detail Routing for Signal Integrity, Timing and Design for Yield
• Wire Editing
• Preventing and Fixing Signal Integrity Problems
• Metal Fill
• Verification
• Engineering Change Orders
• Writing Out a Design
• Challenges of Advanced Nodes in Implementation
• Innovus Database Access Commands
• Foundation Flow Scripts

Audience

• CAD Engineers
• Chip Designers
• Physical Layout Designers

Prerequisites

You must have experience with or knowledge of the following:

• Design methodology

Related Courses

• Innovus Implementation System (Hierarchical)
• Innovus Clock Concurrent Technology for Clock Tree Synthesis
• Tempus Signoff Timing Analysis and Closure

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