Innovus Implementation System (Block) Training

Length: 23 hours

Become Cadence Certified

Course Description

Note: This course is based on the default user interface and not the Stylus Common User Interface. We recommend you check with your design team or Cadence AE before selecting this course instead of the course Innovus Block Implementation with Stylus Common UI. If there is not a clear preference, please select the Innovus Block Implementation with Stylus Common UI course.

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In this course, you learn how to use the Innovus^™ Implementation System software to achieve the best power, performance and area (PPA) for your design. You learn several techniques for floorplanning and placement using the GigaPlace^™ solver-based placement while implementing timing closure strategies with a multi-threaded, layer-aware timing and power-driven optimization engine to reduce dynamic and leakage power. You will learn how to set up and run the concurrent clock and datapath optimization engine to enhance cross-corner variability and boost performance with reduced power.

You run the slack-driven router with track-aware timing optimization which enables you to achieve the multiple objectives that are a part of today's design requirements. You will learn how to diagnose and fix routing violations as well as explore challenges and solutions for design implementation in nodes that are 20nm and below.

Other topics in this course include using database access commands, wire editing, ECOs, and physical verification.

Learning Objectives

After completing this course, you will be able to:

• Import and floorplan a design
• Run placement and optimization using GigaPlace technology
• Plan, route and analyze the power
• Run timing analysis and debug results
• Create clock trees and concurrently run datapath optimization
• Run optimization for power, performance and area
• Run the slack-driven router with track-aware timing optimization
• Run global and detail routing for timing and signal integrity
• Debug routing violations
• Create and edit wires interactively
• Run ECOs on a design
• Address 20nm (and below) challenges as a result of Multi-Pattern Technology (MPT)
• Run design verification for geometry, connectivity, and, antenna
• Run database access commands

Software Used in This Course

• Digital Design Implementation System

The software includes Genus Synthesis Solution, Joules, and Innovus Implementation System.

Software Release(s)

DDI231

Modules in this Course

• Innovus Implementation System Overview
• Design Import and Customizing the Innovus Implementation System Environment
• Selecting and Highlighting Objects in the Design
• Floorplanning the Design
• Planning Power
• Routing Power with Special Route
• Running Placement Optimization
• Scan Optimization and Reordering
• Analyzing Route Feasibility with Early Global Router
• Multi-Mode Multi-Corner Analysis
• Extracting Parasitics and Running Timing Analysis
• Power, Performance and Area Optimization
• Implementing the Clock Tree
• Detail Routing for Signal Integrity, Timing, Power and Design for Yield
• Wire Editing
• Preventing and Fixing Signal Integrity Problems
• Verification
• Engineering Change Orders
• Writing Out a Design
• Challenges of Advanced Nodes in Implementation
• Innovus Database Access Commands

Audience

• CAD Engineers
• Chip Designers
• Physical Layout Designers

Prerequisites

You must have experience with or knowledge of the following:

• Design methodology

Related Courses

• Innovus Implementation System (Hierarchical)
• Innovus Clock Concurrent Technology for Clock Tree Synthesis
• Tempus Signoff Timing Analysis and Closure

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.

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