Essential SystemVerilog for UVM Training

Length: 1 Day (8 hours)

Course Description

Universal Verification Methodology (UVM) is the IEEE class-based verification library and reuse methodology for SystemVerilog. Learning UVM requires a good knowledge of SystemVerilog classes and an understanding of key object-oriented design techniques.

This course prepares the student for the Cadence UVM class by reviewing SystemVerilog classes and key object-oriented design principles and techniques. The course first reviews basic SystemVerilog classes, including randomization and constraints, followed by static properties and methods. We then explore inheritance, polymorphism, casting and virtual methods. We review aggregate classes and define the differences between reference, shallow and deep operations. We connect class instances to DUT ports using virtual interfaces. Finally, the course shows you how to create a hierarchy of verification components using instance names, parent pointers and reference connections.

Learning Objectives

After completing this course, you will be able to:

• Declare and instantiate SystemVerilog classes, including the use of static members, inheritance, aggregation, randomization and constraints.
• Use inheritance effectively, including polymorphism, casting, and virtual methods.
• Create robust, reusable class methods, exploiting inheritance, polymorphism and aggregation, and using key Object-Oriented techniques such as reference, shallow and deep operations.
• Create a class-based verification component hierarchy using instance names and parent pointers.

Software Used in This Course

• XCELIUMS2403

Software Release(s)

XCELIUMS2403

Modules in this Course

• Basic Classes and Randomization
  • Declaring and using class instances
  • Instance names and policies
  • Randomization and constraints
  • Constraint ordering
• Overview of DUT for Lab Exercises
• Static Properties and Methods
• Inheritance and Polymorphism
  • Inheritance and constructors
  • Polymorphism and casting
  • Casting and virtual methods
• Aggregate Classes
  • Reference, shallow and deep operations
  • Cloning
• Components
  • Standard verification component architecture
  • Instance names and parent pointers
  • Simple reference connections
• DUT Connection
  • Interfaces review
  • Virtual interfaces
• Building a Verification Component
• Sequencer, driver and monitor
• Agent
• Instantiation and connection

Audience

• Design and verification engineers seeking to learn UVM

Prerequisites

You must have experience with or knowledge of the following:

• SystemVerilog

Related Courses

• SystemVerilog for Design and Verification
• SystemVerilog Accelerated Verification with UVM

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