Cadence RTL-to-GDSII Flow Training

Length: 2 Days (16 hours)

Become Cadence Certified

Course Description

Note: This course is highly recommended for onboarding new employees (including new college graduates) to learn the complete RTL-to-GDSII flow and get hands-on experience using Cadence tools.

In this course, you learn how to implement a design from RTL-to-GDSII using Cadence^® tools. You will start by coding a design in VHDL or Verilog. You will simulate the coded design, followed by design synthesis and optimization. You will then run equivalency checks at different stages of the flow. After synthesizing the design, you will floorplan, and place-and-route the synthesized netlist while meeting timing. You will run a gate-level simulation throughout the flow. Finally, you will write out a GDSII file.

Learning Objectives

After completing this course, you will be able to:

• Code a design in Verilog to the design specification that is provided
• Compile, elaborate and simulate your design
• Synthesize your design
• Design for test
• Run equivalency checking at different stages of the flow
• Floorplan a design
• Run placement, optimization, clock tree synthesis, and routing on your design
• Run signoff checks to make sure that the design chip can be fabricated
• Write out a GDSII

Software Used in This Course

• Xcelium^™ Simulator (XCELIUM2309)
• Integrated Metrics Center (VERISIUM MANAGER 2309)
• Genus^™ Synthesis Solution (DDI231)
• Cadence Modus DFT Software Solution (MODUS231)
• Conformal^® Equivalence Checker (CONFRML232)
• Innovus™ Implementation System (DDI231)
• Tempus^™ Timing Signoff Solution (SSV231)
• Voltus^™ Power Signoff Solution (SSV231)
• Quantus^™ RC Extraction (SSV231)

The software DDI includes Genus Synthesis Solution, Joules^™, and the Innovus Implementation System.

Software Release(s)

XCELIUM2309, VMANAGER2309, MODUS231, CONFRML232, DDI231, SSV231

Modules in this Course

• Design Specification and RTL Coding
• Design Simulation Using the Xcelium Simulator
• Code Coverage Using the Integrated Metrics Center
• The Synthesis Stage
• The Test Stage
• The Equivalency Checking Stage
• The Implementation Stage
• Gate-Level Simulation
• Timing Analysis and Debug

Audience

• University students
• New hires who need to ramp up on Cadence tools
• Design engineers or verification engineers who need to learn the Cadence flow

Prerequisites

You must have:

• Knowledge of UNIX/Linux
• Basic knowledge of programming languages, for example, VHDL/Verilog/SV in order to code a simple design

Related Courses

• Xcelium Simulator
• Verilog Language and Application
• Design for Test Fundamentals
• Genus Synthesis Solution
• Innovus Implementation System
• Tempus Signoff Timing Analysis and Closure
• Conformal Equivalence Checking

Free Online Training Bytes (Videos)