Metric Driven Verification using Cadence vManager

Learning Objectives

After completing this course, you will be able to:In this course, you

• Define and review the Cadence Metric Driven Verification (MDV) methodology
• Use the MDV in a verification project
• Recognize the importance of verification planning and develop a vPlan
• Explore the vManager tool and identify the various centers
• Set up the server profile for the vManager server
• Use vManager Planning to create a verification plan (vPlanx) format
• Apply a reusable vPlan
• Create a regression run with a Verification Session Input File (VSIF)
• Explore Metrics analysis using the Analysis Center
• Run regressions using vManager and map coverage
• Analyze metrics and perform coverage correlation and ranking
• Recognize the usefulness of the Web dashboard, vAPI, Sever Security Authentication and Authorization
• Generate project reporting and charting in tracking centers

Software Used in This Course

• vManager 20.03
• Xcelium 20.03

Software Release(s)

vManager Linux Client, VMG001, QTY 1, vManager Web Client, VMG002, QTY 1, vManager Linux Client, VMG005, QTY 5, vManager Project Server VMG100, vManager Integration Server VMG200, vManager App: Multi-Project, VMGA01, VMGHA01

Modules in this Course

• What Is Metric Driven Verification (MDV)?
• vManager – An Introduction
• Setting Up the vManager Server
• What Is Verification Planning?
• Creating a vPlan Using vManager Planning
• vPlan Analysis
• Running Regressions and Its Infrastructure
• Regression Center and Session-Related Tasks
• Collecting Runs
• Analysis Center and Runs Analysis
• Analysis Center and Metrics Analysis
• Integration of JasperGold^® with vManager
• Tracking Progress to Project Closure: Tracking and Charting
• Server Security and Web Portal
• vAPI
• Appendix: vPlan Visitor
• Appendix: The Integration Process and the Automation of Regression Flow

Audience

• Verification engineers building coverage-driven verification plans
• Architects
• Testbench architects
• Verification and Design engineers

Prerequisites

You must have experience with the following:

• UVM Methodology and OVM Methodology or
• Experience with SystemVerilog or e, constrained random or SystemVerilog Assertions (SVA)
• Basic working knowledge of coverage, including functional coverageReplace this text

Or you must have completed the following course:

• Foundations of Metric Driven Verification

Related Courses

• SystemVerilog Advanced Verification Using UVM
• Xcelium Integrated Coverage
• Foundations of Metric Driven Verification - this course is a desirable pre-requisite since it gives a fantastic overview of the MDV Methodology which makes this current course on vManager tool learning easy

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