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        • Power Analysis
        • Constraints and CDC Signoff
        • Silicon Signoff and Verification
        • Library Characterization
        • Test
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        • Circuit Design
        • Circuit Simulation
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        • Layout Verification
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        • RF / Microwave Solutions
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        • Debug Analysis
        • Emulation
        • Formal and Static Verification
        • FPGA-Based Prototyping
        • Planning and Management
        • Simulation
        • Software-Driven Verification
        • Verification IP
        • System-Level Verification IP
        • Flows
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        • Interface IP
        • Denali Memory IP
        • Tensilica Processor IP
        • Analog IP
        • System / Peripherals IP
        • Verification IP
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        • IC Package Design
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • Flows
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        • Electromagnetic Solutions
        • RF / Microwave Design
        • Thermal Solutions
        • System Analysis Resources Hub
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        • PCB Layout
        • Library and Design Data Management
        • Analog/Mixed-Signal Simulation
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
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  • Metric Driven Verification Using Cadence vManager



Metric Driven Verification Using Cadence vManager

Online Courses
Instructor-Led Schedule
Date Version Country Location
10 - 12 May 2021 20.03 France Vélizy-Paris
France
ENROLL
10 - 12 May 2021 20.03 Germany EMEA-Blended
Germany
ENROLL
10 - 12 May 2021 20.03 Germany Feldkirchen-Munich
Germany
ENROLL
10 - 12 May 2021 20.03 Israel Petah-Tikva-Tel Aviv
Israel
ENROLL
10 - 12 May 2021 20.03 Sweden Kista-Stockholm
Sweden
ENROLL
10 - 12 May 2021 20.03 United Kingdom Of Great Britain And Northern Ireland Bracknell-London
United Kingdom Of Great Britain And Northern Ireland
ENROLL
Scheduled upon demandOn demand EXPRESS INTERESTINQUIRE
Version Region
20.03 Online ENROLL
Other Versions Online EXPRESS INTERESTINQUIRE

Length: 3 days

Course Description

Cadence® vManager™ is a revolutionary tool which is completely based on the Metric Driven Verification methodology. It is a complete database-driven architecture of Incisive® Enterprise Manager with powerful new features for tracking verification progress. vManager provides verification management, command and control, enabling predictability, and productivity and quality to the verification environment. It improves verification scalability and helps you deliver verification projects sooner and with higher quality.

Learning Objectives

After completing this course, you will be able to:

  • Define and review the Cadence Metric Driven Verification (MDV) methodology
  • Use the MDV in a verification project
  • Recognize the importance of verification planning and develop a vPlan
  • Explore the vManager tool and identify the various centers
  • Set up the server profile for the vManager server
  • Use vManager Planning to create a verification plan (vPlanx) format
  • Apply a reusable vPlan
  • Create a regression run with a Verification Session Input File (VSIF)
  • Explore Metrics analysis using the Analysis Center
  • Run regressions using vManager and map coverage
  • Analyze metrics and perform coverage correlation and ranking
  • Recognize the usefulness of the Web dashboard, vAPI, Sever Security Authentication and Authorization
  • Generate project reporting and charting in tracking centers

Software Used in This Course

  • vManager 20.03
  • Xcelium 20.03

Software Release(s)

vManager Linux Client, VMG001, QTY 1, vManager Web Client, VMG002, QTY 1, vManager Linux Client, VMG005, QTY 5, vManager Project Server VMG100, vManager Integration Server VMG200, vManager App: Multi-Project, VMGA01, VMGHA01

Modules in this Course

  • What Is Metric Driven Verification (MDV)?
  • vManager – An Introduction
  • Setting Up the vManager Server
  • What Is Verification Planning?
  • Creating a vPlan Using vManager Planning
  • vPlan Analysis
  • Running Regressions and Its Infrastructure
  • Regression Center and Session-Related Tasks
  • Collecting Runs
  • Analysis Center and Runs Analysis
  • Analysis Center and Metrics Analysis
  • Tracking Progress to Project Closure: Tracking and Charting
  • vAPI
  • vManagerHigh Availability Platform/Server
  • WebPortal and Server Security
  • vManagerMonitor
  • AppendixA: vManager Batch Mode
  • AppendixB: MessageBroker

Audience

  • Verification engineers building coverage-driven verification plans
  • Architects
  • Testbench architects
  • Verification and Design engineers

Prerequisites

You must have experience with the following:

  • UVM Methodology and OVM Methodology or
  • Experience with SystemVerilog or e, constrained random or SystemVerilog Assertions (SVA)
  • Basic working knowledge of coverage, including functional coverageReplace this text

Or you must have completed the following course:

  • Foundations of Metric Driven Verification

Related Courses

  • SystemVerilog Advanced Verification Using UVM
  • Xcelium Integrated Coverage
  • Foundations of Metric Driven Verification - this course is a desirable pre-requisite since it gives a fantastic overview of the MDV Methodology which makes this current course on vManager tool learning easy

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.

Course ID: 86132

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"One of the best technical trainings I had in 12 years."

Clemens Suessmuth, NXP Semiconductors

"The course has been very helpful because it has given me a practical and extensive overview on how to put into effect the MDV paradigm. I will definitely consider how to apply it to the project I am currently working on."

Elia Conti, CERN

"Competent trainer, nice, fruitful class. The course gave a broad overview of the methodology and the respective tool features. The instructor knew the big picture of the topic very well and was also able to answer detailed questions competently."

"A very good training. It was perfect for me."

Gert Marnaus, NXP Semiconductors

"Short and good overview of the vManager tool."

Tobias Pontesegger, Infineon Technologies

"Very well-structured and well-presented course. The instructor was always able to interact on questions."

Joerg Keber, NXP Semiconductors

"Perfect match. I have not been disappointed. It's great that the trainer tells also from his experience that he made with different users/customers. The lecture manual will be a great reference for me in the next years."

Thorsten Klose, Infineon Technologies

"The course was helpful to get started using the tool, and already provides insight in more advanced features."

Patrick Forster, Texas Instruments

"It was perfect."

Artem Rychkov, Progress Microelectronics

"I really enjoyed the course. The sessions are well prepared and easy to understand. The quality of the videos is good."

Horst Bauer, Infineon

 
 

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