RTL designers are challenged by increasingly complex designs. They’re also expected to deliver higher quality RTL to verification teams under tight schedules. And teams want to expose bugs as soon as possible—to reduce the cost per bug—which puts additional pressure on designers.
Conventional methods of design bring-up using unit-level testbenches are no longer the optimal way to address these challenges. Design teams are realizing that throwaway unit-level testbenches can be replaced with a methodology that combines structural analysis and formal behavior exploration to rapidly bring up designs and catch bugs as soon as possible. What’s more, reusable properties can be handed off to other design and verification teams and can easily be leveraged in future iterations of the same design.
This webinar introduces RTL designers to this powerful methodology—and covers best practices for getting the most out of RTL design bring-up using the Cadence® JasperGold® Formal Verification Platform. Attendees will leave the webinar with knowledge that will enable them to achieve design bring-up goals more thoroughly and efficiently, producing higher quality RTL in the process.
RTL design bring-up challenges
When is your design ready to handoff to verification?
An advanced design bring-up methodology using the JasperGold® platform