JasperGold Formal Fundamentals

Length: 2 1/2 days (20 Hours)

Digital Badge Available

Course Description

This course is intended for people with little or no experience in Formal Analysis (FA) and JasperGold^®. This course illustrates, in a very pragmatic way, how to code SVA properties that are efficient for Formal Analysis. Formal Analysis is a completely different paradigm to older and more widely adopted methods of verification like simulation. As such, the fundamental objectives, capabilities, limitations, setup and initialization requirements, in addition to analysis and interpretation of results, need to be well understood before we can make effective use of FA tools and specialized JasperGold Apps. Formal is capable of much more than simulation alone and can deliver optimization techniques often needed to be applied to get conclusive results within realistic timescales. These techniques are extremely difficult to discover or pick up "as one goes along" without training or expert assistance. Anyone can run an FA tool but experience is needed to get conclusive results in a realistic timeframe that are completely understood. This course is intended as a shortcut to gaining that experience. The course has 60% lectures and 40% hands-on labs.

Learning Objectives

After completing this course, you will be able to:

• Define reusable, functionally correct SVA properties that are efficient for formal tools
• Set up, run and analyze results from Formal Analysis having identified designs upon which formal is likely to be successful
• Understand formal complexity issues and how to overcome them
• Create a complete formal environment from scratch given only a DUT functional specification
• Set up and run Superlint and X-Propagation Apps

Software Used in This Course

• JasperGold
• VIPCAT 11.3

Software Release(s)

JG2109

Modules in this Course

Formal Friendly SVA Coding

• Identify SVA which is likely to be inefficient
• Create Auxiliary Code (HDL helper code) to assist when writing properties
• Recognize problems that cannot be solved by SVA alone
• Replace inefficient SVA code with a combination of simple properties and simple auxiliary code

Introduction to Formal Analysis

• Contrast Formal with Dynamic
• Describe Formal Analysis terminology
• Describe how Formal tools work
• Explain factors affecting the quality of results
• Describe the limitations of Formal Analysis tools
• Recognise initialization issues
• Understand different kinds of formal use models and goal

JasperGold Expert System (JGES)

• Knowledge-Based System
• Client-Based System
• Viewing and using recommendations

JasperGold Apps Usage: Applying DLFA Flow

• Identify focus areas for Formal Analysis
• Design Level Formal Analysis (DLFA) flow phases, setup, initialization, stopats, etc.
• Using ProofGrid to distribute jobs to server farms
• Intro to ProofMaster in JasperGold
• Debug hand-off
• Constraint management and debugging
• Recommendations
• Where to get help

Visualize

• What is Visualize?
• Visualize Flow
• Visualize GUI
• Visualize Features

Overview of Formal Analysis Use Models

• Explain how Formal Verification differs from Simulation
• Use Formal Analysis for design exploration
• Use Formal Analysis to prove user defined functional properties
• Use Formal Analysis to perform Deep Bug Hunting (DBH)
• Apply each of the different JasperGold Apps to obtain verification closure

Causes of Complexity

• Understand contributing factors to formal complexity
• Understand what adds state to the proof and how to reduce state
• Use the JasperGold tool features to understand formal complexity

Generic Complexity Reduction Methods

• How to simplify an environment
• Functional, value and bitwise splitting of properties to improve performance
• Structural changes
• Black-boxing
• Complexity tool aids - Complexity Manager and Formal Profiler

Superlint App

• Set up and run the JasperGold Superlint App to perform the automated Formal checks which you desire
• Analyze the results from the automated formal checks and debug CEXs
• Define, export and import waivers for specific checks which are expected to fail

Abstractions

• Differentiate between what is an abstraction and what is a reduction
• Use abstraction mechanisms to greatly reduce the time taken for a formal proof
• Apply IVAs to choose arbitrary configurations
• Apply Reset Value Abstractions (RVAs)
• Apply counter abstractions

XPROP App

• Use the XPROP App to detect, debug and fix X-propagation issues for a variety of X-sources and destinations
• Use the –precond option to prevent real X-prop problems being masked by the waiving of false negatives

The Verification Completeness Problem

• Review verification methodologies
• Examine case study highlighting the verification completeness problem
• State techniques for minimizing risk of verification holes
• States the merits of each verification technique

Property Development Introduction

• Overcoming the "blank page syndrome"
• Who writes properties and when?
• Guidelines for writing properties
• Categories of properties
• Property development process
• Need for both checks and coverage

Interface Property Development

• Develop black-box protocol properties
• Enumerate a finite set of fundamental behaviors for features extracted from a verification plan
• Enumerate a finite set of protocol categories with which common protocols are associated
• Identify the subset of fundamental behaviors exhibited by a given protocol category
• Use these fundamental behaviors to drive the development of the protocol properties
• General vs. specific properties and why specific properties may be undesirable

Audience

• Design and Verification Engineers

Prerequisites

You must have one month of experience writing properties with SVA.

Or, you must have completed the following course:

NOTE: This course is a subset of the online only course #86235 titled SVA, Formal and JasperGold Fundamentals for Designers. This course does not cover basic SVA syntax and principles.

Related Courses

• JasperGold Formal Expert
• SVA, Formal and JasperGold Fundamentals for Designers
• SystemVerilog Assertions

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