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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • Allegro X Design Platform
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        • Hyperscale Computing
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        • Photonics
        • RF / Microwave
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        • Hyperscale Computing
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  • Allegro PCB Editor Intermediate Techniques



Allegro PCB Editor Intermediate Techniques

Online Courses
Instructor-Led Schedule
Date Version Country Location
21 - 22 Jul 2022 17.4-2019QIR2 Sweden Kista-Stockholm
Sweden
ENROLL
21 - 22 Jul 2022 17.4-2019QIR2 United Kingdom Of Great Britain And Northern Ireland Bracknell-London
United Kingdom Of Great Britain And Northern Ireland
ENROLL
18 - 19 Oct 2022 17.4-2019QIR2 Germany Feldkirchen-Munich
Germany
ENROLL
21 - 22 Nov 2022 17.4-2019QIR2 France Vélizy-Paris
France
ENROLL
Scheduled upon demandOn demand EXPRESS INTERESTINQUIRE
Version Region
17.4-2019QIR2 Online ENROLL
17.2-2016QIR6 Online ENROLL
Other Versions Online EXPRESS INTERESTINQUIRE

Length: 2 days (16 Hours)

Digital Badge Available

Course Description

The Allegro® PCB Editor Intermediate Techniques course gives you a deeper understanding of the software and includes features and tips. You apply constraints, autoroute high-speed designs, and work with differential pairs. In this course, you also explore high-speed design rules, create areas in your design that require different routing rules, and generate testpoints. In the task-oriented labs, you use a combination of interactive and automatic tools.

This is the second in a two-course series. You need to complete the Allegro PCB Editor Basic Techniques course before taking this one or have the equivalent work experience.

This course requires the SPB17.4-2019QIR2(S013) software or later.

Learning Objectives

After completing this course, you will be able to:

  • Work with split planes
  • Use the Constraint Manager efficiently
  • Autoroute high-speed designs
  • Create rules and route differential pairs
  • Perform interactive bus routing
  • Perform advanced interactive and automatic routing of critical nets
  • Generate testpoints
  • Place parts based upon design-for-assembly rules
  • Write extract programs
  • Use existing SKILL® programs in the PCB Editor
  • Create designs with split and complex power planes
  • Use the automatic glossing routines

Software Used in This Course

  • Allegro PCB Designer

Software Release(s)

SPB17.4-2019QIR2(S013) or later

Modules in this Course

  • Design for Assembly
  • Interactive Etch Editing
  • Unused Pad Suppression
  • Copper Planes
  • Intermediate Constraints
  • High-Speed Constraint Management
  • Reusing Design Constraints
  • Differential Pairs
  • Glossing
  • Testpoint Generation
  • Extraction of PCB Editor Views
  • Tips and Tricks
  • SKILL Commands in the PCB Editor

Audience

  • CAD Engineers
  • Designers
  • Electrical Engineers
  • Layout Designers
  • PCB Designers
  • PCB Layout Designers

Prerequisites

You must have experience with or knowledge of the following:

  • Board Layout Design

Or you must have completed the following courses:

  • Allegro PCB Editor Basic Techniques.

Related Courses

  • Allegro PCB Editor Basic Techniques
  • Allegro High-Speed Constraint Management

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.

Course ID: 86098

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"This is a great environment for learning, very peaceful and secure. The instructors are knowledgeable and friendly and easy to ask any questions.”

Yogesh Patel, Schneider Electric

"The training was great and satisfying my needs. I especially like the lab and the support of the instructor in doing this lab."

Eslam Sawaby, Valeo

"The course was well prepared and I think that giving us time to do the labs after explanations is a really good way to directly practice our learning. (...) the contents were clear and easy to understand. The teacher was nice and took time for us."

Ruben Guerreiro, Meggitt Sensing Systems

"Very good training."

Hao Li, Incoatec

“Great class, learned a lot. Very well presented, excellent labs with good docs.”

Debra Lefley, Broadcom

“This training was very good. In 15 modules I learned a lot about the PCB Editor, each lesson was finished with some tutorials to practice the work with the tool.”

Volker Rittmann, Incoatec

"Good training."

Fabrice Brossier, Thales Group

"I liked the open discussion about problems in “real life”. I learned good tips and tricks to speed up my daily work."

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