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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • System Design and Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation
          • Formal and Static Verification
          • FPGA-Based Prototyping
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Z1 Enterprise Emulation Platform
          • Protium X1 Enterprise Prototyping Platform
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • System Analysis
        • PRODUCT CATEGORIES
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Sigrity Advanced SI
          • Sigrity Advanced PI
          • RESOURCES
          • System Analysis Resources Hub
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • What's New in Sigrity
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
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      • AI IP Portfolio
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        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
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        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
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        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
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        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
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  • Allegro System Architect



Allegro System Architect

Online Courses
Instructor-Led Schedule
Date Version Country Location
Scheduled upon demandOn demand EXPRESS INTERESTINQUIRE
Version Region
17.4.2019QIR2 Online ENROLL
17.2-2016 Online ENROLL
Other Versions Online EXPRESS INTERESTINQUIRE

Length: 2 days

Course Description

In this course, you learn to use the Allegro® System Architect GXL product in a front-to-back board design flow. You explore a new paradigm in design entry by using a spreadsheet or the table-based System Connectivity Manager. You set up a project, add components and define connectivity. You create a hierarchical design structure, add properties and define routing rules. You run placement, routing and backannotation on the hierarchical design.

Learning Objectives

After completing this course, you will be able to:

  • Create and set up your own project, and use the CDS_SITE variable to customize the setup environment
  • Add components and define connectivity with System Connectivity Manager (SCM), a spreadsheet-based design entry tool
  • Define bypass, pullup/pulldown, and termination requirements; understand how these associated components are handled
  • Create a hierarchical design structure by creating and importing schematic, Verilog, and spreadsheet blocks
  • Use the Constraint Manager to add part and net properties and to define routing rules
  • Transfer the hierarchical design to the Allegro PCB Editor
  • Perform placement, routing and backannotation
  • Create reports and generate a document schematic

Software Used in This Course

  • Allegro Design Authoring
  • Allegro PCB Designer

Software Release(s)

SPB174

Modules in this Course

  • Previewing Completed Projects
  • Project Creation and Setup
  • Working with Components and Connectivity
  • Working with Associated Parts
  • Working with Hierarchical Designs
  • Working with Properties and Electrical Constraints
  • Transferring the Logical Design to a Board
  • Creating Reports and Generating the Document Schematic

Audience

  • Design Engineers
  • Tool Integrators

Prerequisites

There are no prerequisites for this course.

Related Courses

  • Allegro Design Entry HDL Front-to-Back Flow
  • Allegro High-Speed Constraint Management
  • Allegro PCB Librarian

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.

Course ID: 86094

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