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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • System Design and Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation
          • Formal and Static Verification
          • FPGA-Based Prototyping
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Z1 Enterprise Emulation Platform
          • Protium X1 Enterprise Prototyping Platform
          • System VIP
          • RESOURCES
          • Flows
      • IP
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          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
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        • PRODUCT CATEGORIES
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Sigrity Advanced SI
          • Sigrity Advanced PI
          • RESOURCES
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          • Augmented Reality Lab Tools
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  • Allegro High-Speed Constraint Management



Allegro High-Speed Constraint Management

Online Courses
Instructor-Led Schedule
Date Version Country Location
30 - 31 Mar 2021 17.4-2019 France EMEA-Blended-France
France
ENROLL
30 - 31 Mar 2021 17.4-2019 United Kingdom Of Great Britain And Northern Ireland EMEA-Blended-UK
United Kingdom Of Great Britain And Northern Ireland
ENROLL
23 - 24 Jun 2021 17.4-2019 France EMEA-Blended-France
France
ENROLL
Scheduled upon demandOn demand EXPRESS INTERESTINQUIRE
Version Region
17.4-2019 Online ENROLL
17.2-2016QIR6 Online ENROLL
Other Versions Online EXPRESS INTERESTINQUIRE

Length : 2 days

Digital Badge Available

Course Description

This Engineer Explorer course is designed around advanced topics and exploration of the software. This course does not cover basic operations. If you are not actively using the software, then you need to complete the Allegro® PCB Editor, the Allegro Package Designer, or the Allegro Design Entry HDL Front-to-Back Flow course.

In this course, you apply and verify high-speed constraints across a design process. You learn to schedule nets, control impedance on nets, control the propagation delay from your drivers to receivers, and match the propagation delay of driver and receiver pairs

Learning Objectives

After completing this course, you will be able to:

  • Define specific net scheduling of high-speed nets
  • Match the propagation delay of nets and connections
  • Define minimum and maximum propagation delays for nets and connections
  • Identify high-speed constraint violations
  • Identify all the high-speed constraints that you can apply to the nets in your designs
  • Create spacing and physical constraints as well as area constraints and class-to-class rules
  • Customize worksheets
  • Create formula-based constraints
  • Create customized constraints using the SKILL® programming language

Software Used in This Course

  • Allegro PCB Designer
  • Allegro PCB High Speed Option

Software Release(s)

SPB17.2-2016QIR6(S038)

Modules in this Course

  • Setting Up Your Design
  • Constraint Management
  • Differential Pairs
  • Wiring Control
  • Relative Propagation Delay
  • Propagation Delay
  • Impedance and Etch Length
  • System-Level Constraints
  • DDR Constraints on a Schematic
  • Physical and Spacing Constraints
  • Formulas and Custom Constraints
  • Return Path Checking
  • Debugging Problems

Audience

  • Logic Designers
  • PCB Designers

Prerequisites

You must have experience with or knowledge of the following tools:

  • Allegro PCB Editor or Allegro Design Entry HDL

Related Courses

  • Allegro PCB Editor Intermediate Technques
  • Allegro Design Entry HDL Front-to-Back Flow

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.

Course ID: 86081

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"Very beneficial class with many detailed side information."

Sascha Kley, Lippert Adlink Technology

"Enough time to solve all questions and problems. Well done teaching speed, all in all positive. Great introduction examples prior to book explanations."

Sinisa Rubil, Automotive Lighting

 
 

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