Length : 2 days
Course Description
This Engineer Explorer course is designed around advanced topics and exploration of the software. This course does not cover basic operations. If you are not actively using the software, then you need to complete the Allegro® PCB Editor, the Allegro Package Designer, or the Allegro Design Entry HDL Front-to-Back Flow course.
In this course, you apply and verify high-speed constraints across a design process. You learn to schedule nets, control impedance on nets, control the propagation delay from your drivers to receivers, and match the propagation delay of driver and receiver pairs.
Learning Objectives
After completing this course, you will be able to:
- Define specific net scheduling of high-speed nets
- Match the propagation delay of nets and connections
- Define minimum and maximum propagation delays for nets and connections
- Identify high-speed constraint violations
- Identify all the high-speed constraints that you can apply to the nets in your designs
- Create spacing and physical constraints as well as area constraints and class-to-class rules
- Customize worksheets
- Create formula-based constraints
- Create customized constraints using the SKILL® programming language
Software Used in This Course
- Allegro PCB Designer
- Allegro PCB High Speed Option
Software Release(s)
SPB17.4-2019
Modules in this Course
- Setting Up Your Design
- Constraint Management
- Differential Pairs
- Wiring Control
- Relative Propagation Delay
- Propagation Delay
- Etch Length, Impedence, Via Control
- System-Level Constraints
- DDR Constraints on a Schematic
- Physical and Spacing Constraints
- Formulas and Custom Constraints
- Return Path Checking
Audience
- Logic Designers
- PCB Designers
Prerequisites
You must have experience with or knowledge of the following tools:
- Allegro PCB Editor or Allegro Design Entry HDL
Related Courses
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
