Allegro High-Speed Constraint Management

After completing this course, you will be able to:

• Define specific net scheduling of high-speed nets
• Match the propagation delay of nets and connections
• Define minimum and maximum propagation delays for nets and connections
• Identify high-speed constraint violations
• Identify all the high-speed constraints that you can apply to the nets in your designs
• Create spacing and physical constraints as well as area constraints and class-to-class rules
• Customize worksheets
• Create formula-based constraints
• Create customized constraints using the SKILL^® programming language

• Allegro PCB Designer
• Allegro PCB High Speed Option

• Setting Up Your Design
• Constraint Management
• Differential Pairs
• Wiring Control
• Relative Propagation Delay
• Propagation Delay
• Impedance and Etch Length
• System-Level Constraints
• DDR Constraints on a Schematic
• Physical and Spacing Constraints
• Formulas and Custom Constraints
• Return Path Checking
• Debugging Problems

• Logic Designers
• PCB Designers

You must have experience with or knowledge of the following tools:

• Allegro PCB Editor or Allegro Design Entry HDL

• Allegro PCB Editor Intermediate Technques
• Allegro Design Entry HDL Front-to-Back Flow

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.