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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • Allegro X Design Platform
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
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      • Computational Fluid Dynamics
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        • Photonics
        • RF / Microwave
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        • Automotive
        • Hyperscale Computing
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  • Allegro High-Speed Constraint Management



Allegro High-Speed Constraint Management

Online Courses
Instructor-Led Schedule
Date Version Country Location
11 - 12 Oct 2022 17.4-QIR4 Germany Feldkirchen-Munich
Germany
ENROLL
15 - 16 Nov 2022 17.4-QIR4 France Vélizy-Paris
France
ENROLL
Scheduled upon demandOn demand EXPRESS INTERESTINQUIRE
Version Region
17.4-QIR4 Online ENROLL
17.2-2016QIR6 Online ENROLL
Other Versions Online EXPRESS INTERESTINQUIRE

Length: 2 days (16 Hours)

Digital Badge Available

Course Description

This Engineer Explorer course is designed around advanced topics and exploration of the software. This course does not cover basic operations. If you are not actively using the software, then you need to complete the Allegro® PCB Editor, the Allegro Package Designer, or the Allegro Design Entry HDL Front-to-Back Flow course.

In this course, you apply and verify high-speed constraints across a design process. You learn to schedule nets, control impedance on nets, control the propagation delay from your drivers to receivers, and match the propagation delay of driver and receiver pairs.

Learning Objectives

After completing this course, you will be able to:

  • Define specific net scheduling of high-speed nets
  • Match the propagation delay of nets and connections
  • Define minimum and maximum propagation delays for nets and connections
  • Identify high-speed constraint violations
  • Identify all the high-speed constraints that you can apply to the nets in your designs
  • Create spacing and physical constraints as well as area constraints and class-to-class rules
  • Customize worksheets
  • Create formula-based constraints
  • Create customized constraints using the SKILL® programming language
  • Create return path constraints

Software Used in This Course

  • PA3100 - Allegro PCB Designer
  • PA3110 - Allegro PCB High-Speed Option
  • PS3500 - Allegro PCB Routing Option (or equivalent)

Software Release(s)

SPB17.4-2019QIR4 or later

Modules in this Course

  • Setting Up Your Design
  • Constraint Management
  • Differential Pairs
  • Wiring Control
  • Relative Propagation Delay
  • Propagation Delay
  • Etch Length, Impedence, Via Control
  • System-Level Constraints
  • Parallel Bus Constraints on a Design Entry HDL Schematic
  • Parallel Bus Constraints on a System Capture Schematic
  • Physical and Spacing Constraints
  • Formulas and Custom Constraints
  • Return Path Checking

Audience

  • Logic Designers
  • PCB Designers

Prerequisites

You must have experience with or knowledge of the following tools:

  • Allegro PCB Editor or Allegro Design Entry HDL

Related Courses

  • Allegro PCB Editor Intermediate Technques
  • Allegro Design Entry HDL Front-to-Back Flow

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.

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Course ID: 86081

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"Very beneficial class with many detailed side information."

Sascha Kley, Lippert Adlink Technology

"Enough time to solve all questions and problems. Well done teaching speed, all in all positive. Great introduction examples prior to book explanations."

Sinisa Rubil, Automotive Lighting

 
 
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